Mitsubishi Electric Corporation

Mitsubishi Electric Research Laboratories, Inc.

Kenya Sugihara

Hideo Yoshida

Yoshikuni Miyata

Wataru Matsumoto

Kazuo Kubo

Kenji Ishii

Takashi Sugihara

Takashi Mizuochi

Yoshiaki Konishi

Kiyoshi Onohara

Takafumi Fujimori

Seidai Takeda

Toshiaki Akino

Kyohei Suwabe

Yumiko Katayama

Included in an inference device of a neural network are: a memory for storing a layer on an input side and weight data for generating a matrix multiplication using the layer on the input side; and a processor for generating a layer on an output side, by using the layer on the input side and the weight data for generating the matrix multiplication using the layer on the input side, in which, out of a plurality of rows and columns including zero elements and non-zero elements in the weight data, the memory stores only non-zero weights and position information of the non-zero weights and the number of non-zero elements in each of the rows is approximately the same. Therefore, it is possible to reduce the amount of memory in a memory for storing learned weight data of a weight matrix. It is also possible to reduce the amount of memory of a memory for storing positions of non-zero weight elements of the weight matrix.

Inference device and method for reducing the memory usage in a weight matrix

An arithmetic device includes a first register that stores input data as values of a plurality of input neurons, a plurality of ports, and a plurality of processing element groups that correspond to the plurality of ports, respectively, and can access the first register through the respective corresponding ports. Each processing element group includes a plurality of processing elements. Each processing element is associated with at least one of a plurality of output neurons and performs a multiply-and-accumulate computation in which a value of at least one input neuron connected to a corresponding output neuron is multiplied by a weight coefficient and results of multiplication are accumulated.

Arithmetic device

A side information calculating unit () calculates side information for assisting either identification processing or classification processing. When there is a discrepancy between a processing result of either the identification processing or the classification processing, and the side information, the multilayer neural network () changes an output value of an intermediate layer () and performs either the identification processing or the classification processing again.

Identification/classification device and identification/classification method

Provided is an optical transmission/reception device including an error correction decoding unit () for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit () is configured to perform decoding processing using a parity check matrix () of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices () combined with each other, in which the decoding processing is windowed decoding processing that uses a window () over one or more parity check sub-matrices (), and in which a window size of the window () and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit () connected to the error correction decoding device ().

Error correction decoding device and optical transmission/reception device

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.

Error correction device and error correction method

An error correction encoder () includes an interleaver circuit (), encoding circuits () and a deinterleaver circuit (). The interleaver circuit () generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL, IL) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits () apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL) or the two series of yet-to-be-coded bit sequences (IL, IL).

Encoder device, decoder device and transmission apparatus

A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.

Transmitter and receiver, and method of varying a coding rate

An error correction decoding apparatus includes column operatorsand row operatorstoprovided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operatorstogether with row LLRs from the row operatorsto, whereupon the column operatorscalculate a total value zof the received LLR of the received sequence and the row LLRs from the row operatorsto. The row operatorstohold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operatorsand the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators

Error correction decoding apparatus

A likelihood generation apparatus for acquiring a likelihood of a 16QAM signal includes a first likelihood generation unit configured to generate a likelihood of each of two bits of a 16QAM signal point of the 16QAM signal from a relationship of each of an I-axis component and a Q-axis component with a likelihood when the 16QAM signal point is mapped on a constellation diagram, and a second likelihood generation unit configured to generate a likelihood of each of remaining two bits other than the two bits of the 16QAM signal point of the 16QAM signal based on a position of the 16QAM signal point in a lookup table, which is configured to input the I-axis component and the Q-axis component of the 16QAM signal point as arguments, and includes regions acquired by dividing the constellation diagram based on a possible value of each of the bits.

Likelihood generation apparatus and method therefor

There are provided a hard decision value calculator that calculates hard decision values from I-ch and Q-ch coordinates of a received symbol having been subjected to multilevel modulation, and an LLR calculator that approximately calculates LLRs from the I-ch and Q-ch coordinates of the received symbol. In a case where a sign bit of an LLR calculated by the LLR calculator conflicts with a hard decision value calculated by the hard decision value calculator, an LLR corrector inverts the sign bit of the LLR and outputs the sign-bit-inverted LLR as a soft decision value to an error correction decoder.

Soft decision value generating apparatus and method of generating soft decision value

An error correction encoding deviceincludes a sparse matrix computing unitthat computes exclusive OR of a submatrix, in a parity-check matrix, corresponding to an information bit sequence, and the information bit sequence on the basis of the position of 1 in the submatrix to calculate a vector, a fundamental matrix operatorthat calculates a predetermined matrix by performing a predetermined fundamental matrix operation on a submatrix, in the parity-check matrix, corresponding to a parity bit sequence, and a matrix multiplierthat calculates the parity bit sequence by multiplying the predetermined matrix which the fundamental matrix operatorcalculates, and the vector which the sparse matrix computing unitcalculates.

Error correction encoding method and error correction encoding device

A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.

Receiver, transmitter, and communication method

A two-reference-point-pair determining unitdetermines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unitassigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.

LLR computation device and error correction decoding device

An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.

Method and device for estimating input bit error ratio

An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.

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Tokyo, Japan

Kenya Sugihara