Nec Electronics Corporation

Nec Corporation

Renesas Electronics Corporation

Kenya Kobayashi

Hideo Yamamoto

Atsushi Kaneko

Yoshimitsu Murase

Kinya Ohtani

Kensuke Okonogi

Tomohiro Hamajima

Wataru Sumida

Takayoshi Andou

A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions.

Semiconductor device and method for manufacturing the same

A method of manufacturing a semiconductor device, includes forming a first trench and a second trench in a semiconductor region of a first conductivity type simultaneously, forming a gate insulating film and a gate electrode in the first trench, forming a channel region of a second conductivity type in the semiconductor region, forming a source region of the first conductivity type in the channel region, forming a diffusion region of the first conductivity type which has a higher concentration than that of the semiconductor region in a part of the semiconductor region located immediately under the second trench by implanting impurity ions of the first conductivity type through the second trench, and forming a drain electrode in a part of the second trench.

Method of manufacturing a semiconductor device having vertical MOSFET

A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region.

Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof

A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.

A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.

A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.

Semiconductor device having vertical type MOSFET and manufacturing method thereof

A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.

The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFETcomprises a plurality of gate trencheswhich is arranged in stripes, an array which is sandwiched with the plurality of gate trenchesand includes Nsource regionsN+ and Pbase contact regionsP+, and a diode region (anode regionP+) which is formed so as to contact with two gate trenches. The Nsource regionsN+ and the base contact regionsP+ are alternately arranged along a longitudinal direction of the gate trench. Size of the diode region (anode regionP+) corresponds to at least one of the Nsource regionsN+ and two of the Pbase contact regionsP+.

Semiconductor device having trench gate structure

A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.

Method of manufacturing semiconductor apparatus

An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench.

Semiconductor device having vertical MOSFET

An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.

Transistor and method for manufacturing same

In a power semiconductor device including a semiconductor substrate of a first conductivity type, a source region of a second conductivity type formed in a surface portion of the semiconductor substrate, and a drain drift region of the second conductivity type formed in the surface portion of the semiconductor substrate, the drain drift region being apart from the source region, a drain region of the second conductivity type is formed in a surface portion of the drain drift region. The drain region has a larger impurity concentration than the drain drift region. A drain buried region of the second conductivity type is formed immediately below the drain region in the drain drift region. The drain buried region has a larger impurity diffusion region than the drain drift region. A gate insulating layer is formed on the semiconductor substrate between the source region and the drain drift region, and a gate electrode is formed on the gate insulating layer.

Lateral planar type power semiconductor device including drain buried region immediately below drain region and its manufacturing method

An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n&#x2212; epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.

A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.

Growing community of inventors

Kanagawa, Japan

Kenya Kobayashi