Renesas Electronics Corporation

Renesas Electronics Coporation

Kenya Hironaga

Masatoshi Yasunaga

Soshi Kuroda

Hironori Matsushima

Tatsuya Hirai

Akira Yamazaki

Satoshi Yamada

Yuji Fujimoto

Takashi Karashima

Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Method of manufacturing semiconductor device

To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Semiconductor device and method of manufacturing the same

To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Semiconductor device with copper wire having different width portions

To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Manufacturing method of semiconductor device

Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (&#x2212;). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.

Method of inspecting semiconductor device

Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Growing community of inventors

Kanagawa, Japan

Kenya Hironaga