Sun Microsystems, Inc.

Kenway W Tam

Shree Kant

Zhen Wu Liu

Kathirgamar Aingaran

Yuan-Jung D Lin

Poonacha P Kongetira

A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.

Method for performing swap operation and apparatus for implementing the same

A hardware implemented method for resolving collisions of memory addresses of a memory array is provided. In this hardware implemented method, a read memory address is compared with a write memory address. If the read and write memory addresses match, write data is directed from a data input to a data output, whereby the data input is further configured to input the write data to the memory array. A system and a memory chip for resolving collisions of memory addresses of a memory array are also described.

Systems and methods for resolving memory address collisions

A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the pipeline immediately following the first swap request. The first swap request and the second swap request are examined to determine if the first swap request and the second swap request swap a same register.

Method and pipeline architecture for processing multiple swap requests to reduce latency

A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

Efficient implementation of a read scheme for multi-threaded register file

A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Efficient method of data transfer between register files and memories

A first sense amp circuit includes a pre-charge circuit, a keeper circuit, a select device and a driver device. The pre-charge circuit coupled to an input data line, the input data line being coupled to an input of a first inverter. The keeper circuit coupled in parallel with the first inverter. The select device coupled to a discharge path of the first inverter. The driver device coupled in parallel to an output data line of the first inverter.

High speed single ended sense amplifier with built-in multiplexer

A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential. The invertor also includes a pull-down path shutoff device, operatively coupled between the output node and the ground in series with the pull-down device, which is closed during each first phase of a clock signal and which is open during each second phase of the clock signal, and an activation device, operatively coupled between the output node and the series connection of the pull-down device and the pull-down shutoff device, which is closed during each first delayed phase of a delayed clock signal and which is open during each second delayed phase of the delayed clock signal.

Dynamic-to-static convertor and staticized flop including the same

A dynamic signal appearing across the output of a logic circuit is converted into a static signal using a dynamic-to-static conversion method which minimizes glitching in the static output. A pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, is closed while the input node is at the ground potential and is open while the input node is at the precharge potential. Also, a pull-down path shutoff device, operatively coupled between the output node and the ground in series with the pull-down device, is closed during each first phase of a clock signal and is open during each second phase of the clock signal, and an activation device, operatively coupled between the output node and the series connection of the pull-down device and the pull-down shutoff device, is closed during each first delayed phase of a delayed clock signal and is open during each second delayed phase of the delayed clock signal.

Dynamic-to-static convertor method

An improved single ended dynamic sense amplifier circuit for sensing the state of a bitline in a read only memory is disclosed which includes a threshold control circuit coupled to a noise margin circuit and a discharge circuit. A sense node couples the discharge circuit to a precharge circuit and an output circuit. The threshold control circuit maintains a bias on the discharge circuit such that during the precharge phase of operation, the discharge circuit is shut off and then conditionally turned off and on. The inclusion of the threshold control circuit in the disclosed single ended dynamic sense amplifier circuit provides for fully functional operation at supply voltages of close to 1.0 volt.

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Cupertino, CA, United States of America

Kenway W Tam