Qualcomm Incorporated

Kentaro Yamamoto

Dinesh Jagannath Alladi

Balasubramanian Sivakumar

Sean Baker

Liang Zhao

Lei Sun

Liang Dai

Elias Dagher

Ganesh Kiran

Aram Akhavan

Sameer Wadhwa

Lennart Karl Mathe

Behnam Sedighi

Seyed Arash Mirhaj

Omid Rajaee

Masoud Ensafdaran

Li Lu

Changsok Han

Weihua Chen

Xiaoke Wen

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

Gain stabilization

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV) coupled to the first inverter (INV), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV) coupled to the second inverter (INV), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop

Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

Output common-mode control for dynamic amplifiers

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

Apparatus and method for generating reference DC voltage from bandgap-based voltage on data signal transmission line

An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

Alias rejection through charge sharing

Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

Time-to-digital converter (TDC)-based quantizer

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Reducing signal dependence for CDAC reference voltage

In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Excess loop delay compensation (ELC) for an analog to digital converter (ADC)

A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

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San Diego, CA, United States of America

Kentaro Yamamoto