Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kenta Yasufuku

Akira Yamaga

Masanobu Shirakawa

Seiji Maeda

Konosuke Watanabe

Naoto Oshiyama

Katsuya Ohno

Tokumasa Hara

Kenichiro Yoshii

Yasuhiko Kurosawa

Naomi Takeda

Mitsuo Saito

Ryo Yamaki

Naoaki Kokubun

Hiroo Hayashi

Ikuo Magaki

Shigeaki Iwasa

Shohei Onishi

Kosuke Hatsuda

Hiroshi Yao

Kohei Oikawa

Takeshi Ishihara

Atsushi Kunimatsu

Daisuke Iwai

Shirou Fujita

Yohei Hasegawa

Yu Nakanishi

Arata Miyamoto

Tsutomu Owa

Masaki Miyagawa

Tsutomu Unesaki

Goh Uemura

Yoshiki Saito

Akifumi Fukuda

Junpei Kida

A memory system includes a non-volatile memory and a controller including a memory having a lower access latency than the non-volatile memory. The controller is configured to track addresses of data stored in the non-volatile memory that were subject to prior wear leveling processes, in a buffer configured in the memory of the controller, perform a current wear leveling process on data stored in the non-volatile memory, and determine whether an address of the data subject to the current wear leveling process is stored in the buffer, and perform a pinning process to disable overwrite of data stored in the memory of the controller and corresponding to the address.

Memory system

An information storage device includes a storage unit, a control unit, an allocation information storage unit, a QoS parameter storage unit, and a monitoring result storage unit. The control unit creates and manages a logical storage area using the storage area of the storage unit when a storage area allocation request is received. The allocation information storage unit stores allocation information related to logical storage areas. The QoS parameter storage unit stores quality requests expected to be satisfied for a communication for using the logical storage area. The control unit monitors the operating state and characteristics of the storage unit and the communication status, and stores the results in the monitoring result storage unit. The control unit derives internal QoS parameters to be set in the information storage device from the information stored in the allocation information storage unit, the QoS parameter storage unit, and the monitoring result storage unit.

Quality of service (QOS) Control in storage device and control system and QOS control method

A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Memory system having semiconductor memory device that performs verify operations using various verify voltages

A memory controller connectable to a semiconductor memory including a plurality of memory areas, includes a counter circuit configured to count a degree of wear of each of the memory areas in response to a memory operation addressed thereto, and a control circuit configured to set a rate of for wear leveling to be performed on the plurality of memory areas based on a total number of memory operations performed thereon, and select whether to perform wear leveling on each of the memory areas based on the rate, the degree of wear counted for the memory area, a first threshold for the degree of wear, and a second threshold for the degree of wear. The second threshold is greater than the first threshold.

Memory controller and memory system

According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.

Memory system and method

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A method of operating the storage device includes maintaining parity data for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restoring the data written to the first memory cells using the parity data.

Storage device that restores data lost during a subsequent data write

According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive logical addresses with the first number of physical addresses which are included in a second number of consecutive physical addresses of the first memory. The controller executes a first updating and a second updating. The first updating includes associating a first physical address among the second number of physical addresses with a first logical address. The second updating includes obtaining a second logical address which is away from the first logical address by a value corresponding to distance information on the basis of origin information and the distance information and associating, with the second logical address, a second physical address which had been associated with the first logical address before the first updating is executed.

Memory system and method for ware leveling

Semiconductor memory device and writing operation method thereof in which first memory cells of a page that are in a first group of contiguous columns are programmed and verified separately from second memory cells of the same page that are in a second group of contiguous columns that does not overlap with the first group

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.

A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.

Semiconductor memory device and writing operation method thereof

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Kanagawa, Japan

Kenta Yasufuku