Renesas Electronics Corporation

Renesas Technology Corp.

Kenta Morishima

Naoki Kato

Yasuo Sugure

A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address translation circuit is provided. When a task so programmed to have a data area in the first memory is transferred to the second memory and executed by the second CPU, the address translation circuit carries out the following processing: the address translation circuit translates an address outputted from the second CPU so that access to the first memory by the task becomes access to the second memory. As a result, the number of access cycles is reduced and degradation in computing capability is avoided when a task is transferred between CPUs for load sharing.

Microcomputer with address translation circuit

In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.

Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors

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Kodaira, Japan

Kenta Morishima