Spansion Llc.

Fujitsu Corporation

Socionext Inc.

Kenta Kato

Mitsuhiro Nagao

Kenji Shibata

Satoru Kawamoto

Takaaki Furuyama

Masahiro Niimi

Koji Shimbayashi

Shozo Kawabata

Masahiko Okura

Stewart Wang

Satoru Sugimoto

Katherine Butler

Cheung Nga Tik

A switching circuit includes a first well and a second well formed in a semiconductor substrate; a first transistor being connected with a first node at one end, and the first transistor being formed in the first well; a second transistor being connected with another end of the first node at one end, and connected with a second node at another end, and the second transistor being formed in the second well; and a potential control circuit that connects the second well with the first node during a predetermined period including a period for the first transistor and the second transistor to transition from off to on in a state where potential of the second node is lower than potential of the first node, and connects the second well with the second node after the predetermined period.

Switching circuit and semiconductor memory device

Operational information read out by a read-out sense amplifier () is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section () having a SRAM configuration and the second volatile memory section () configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section () in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (). Thus, the operational information is available in response to attributes of the operational information.

Non-volatile memory device

A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Memory employing independent dynamic reference areas

A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Memory employing separate dynamic reference areas

The present invention provides a voltage generating circuit and a control method thereof which is capable of preventing an increase in the occupied area and suitable for raising the voltage of the power supply in a wide range. This voltage generating circuit comprises a first charge pump unit to which a first clock signal is inputted, wherein the first charge pump unit generates a voltage by pumping a voltage of a first external power supply in stages by a first voltage, a voltage selector that selects the voltage generated by the first charge pump unit or a voltage of a second external power supply in accordance with a voltage selection command signal, a level converter that converts a voltage level of the first clock signal into a second voltage level, and a second charge pump unit to which the second clock signal that has been converted by the level converter is inputted, wherein the second charge pump unit and that generates a voltage and by pumping the selected voltage or the voltage of the second external power supply.

Charge pump to supply voltage bands

A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

Semiconductor device and method of controlling the same

A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

In inputting control information for setting access conditions in a system having a common data bus (), when a predetermined bit string making up an access condition setting command is inputted to predetermined terminals which are not data input/output terminals (S), the predetermined terminals are set as control information input terminals (S) and inputted control information is temporarily maintained in a non-volatile memory device (S). When inputting of control information is completed (S), the control information that has been temporarily maintained is stored in a non-volatile memory region all at once (S). During an access condition setting operation, the data input/output terminals are released (S) and the data bus () is made available to other banks or devices () so that data transfer efficiency of the system can be improved.

Method and apparatus for setting input terminals for receiving control information in a semiconductor memory device

In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.

Non-volatile memory device, and control method of non-volatile memory device

When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S), and read operation information is read out by preferentially using a verify sense amplifieror a high-speed read sense amplifier(S). Upon completion of latching the read operation information (S: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S). Thereafter, rewrite operation information is read out (S). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

Method and apparatus for initialization control in a non-volatile memory device

A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

Voltage detection circuit, semiconductor device, method for controlling voltage detection circuit

During an erase operation, lower decoder groups() and() (i=1 to m) of erase-target sectors are connected, at their respective low voltage power supply terminals (VL), to a first negative voltage supply line (VM) via switches (B) (and, respectively) and a negative bias voltage is supplied to local word lines. The first negative voltage supply line (VM) is connected to a level shift circuit (), and is level-shifted to a voltage at a higher level relative to that of a second negative voltage (VMP) which is output from a negative voltage generator circuit () via a second negative voltage supply line (VMP). An upper decoder group () is connected, at its low voltage power supply terminal (VL), to the second negative voltage line (VMP) via a switch (A) (). All global word lines GWL() (i=0 to m) are biased to the second negative voltage (VMP) by an active signal (ACTB()) at high level supplied to the upper decoder group () and are biased to a lower voltage level relative to the first negative voltage (VM) as a bias voltage to the local word lines.

Non-volatile memory device, and control method therefor

In Step, a bias is applied (ON) to all of vertical rows Z() to Z(). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z() where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z() and Z(). On the sectors in the horizontal rows Z() and Z(), a voltage stress is applied and an access operation is performed. In Step, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z() where the defective sector exists and a bias is applied (ON) to the other vertical rows Z() and Z(). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z() where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z() and Z(). As for the two steps, a voltage stress can be applied once to the sectors other than the defective sector.

Method and apparatus for applying bias to a storage device

A verify sense amplifier () reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (). Upon completion of rewriting, the comparator circuit () outputs a match signal MCH. A selector () outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier () is stored in the volatile data retaining unit (). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit () upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

Method and apparatus for setting operational information of a non-volatile memory

A control method of a semiconductor memory device which enables control of an operation mode including an operation that might become a noise source by using an operation mode including an operation from which the influence of noise should be eliminated, and a semiconductor memory device are provided. First and second operation sections performing independent operations are provided, and a signal output section for outputting a second signal Sand a mode controller section for supplying a control signal Care provided in the second operation section. The control signal Cis outputted from the mode controller section and the signal output section outputs the second signal Sto a memory cell array, thus performing a second operation. A predetermined first signal SSis supplied to the signal output section from the first operation section, thus delaying an output response of a predetermined second signal. While the control signal Cis outputted from the mode controller section, the supply of the predetermined second signal to the memory cell array can be delayed. The influence of state transition in the second operation on the operation state of the first operation can be eliminated.

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Kasugai, Japan

Kenta Kato