Intel Corporation

Hewlett-packard Company

Altera Corporation

Tabula, Inc.

Agilent Technologies, Inc.

Kent R Townley

Christopher D Ebeling

Pablo Martin Rodriguez

Andrew Edward Caldwell

Hamish T Fallside

Prasun K Raha

Dan Stotz

Michael Glenn Wrighton

Alper Ilkbahar

Gayvin E Stong

David B Hollenbeck

Josef A Dvorak

Brian Cardanha

Ricky L Pettit

Raymond W Rosenberry

A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Clock management block

An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.

Implementation of related clocks

A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

Dynamic circuits and static latches with low power dissipation

An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)&times;f , for a natural number M and reference clock signal frequency f . The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to f with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.

Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one

A method and apparatus for post-driving and pre-driving a terminated bus that shortens dead cycles on a bus during bus master change-overs. In one embodiment, a first bus agent giving up control of the bus drives the bus to termination voltage levels during a first portion of the dead cycle. A second bus agent gaining control of the bus also drives the bus to termination voltage levels during a last portion of the dead cycle. For the time period between the first portion and the second portion, termination components such as resistors or transistors maintain the bus at termination voltage levels. By driving the bus to termination voltage levels with bus agents, bus transients are settled more quickly than with termination components alone, which improves performance of the bus over configurations pulled to termination voltage levels with termination components alone.

System for post-driving and pre-driving bus agents on a terminated data bus

The inventive mechanism provides a hysteresis margin to a comparator. The inventive mechanism generates two different voltage values, one high level and one low level, which forms the noise margin. The mechanism will select the proper level based on the output of the comparator. The comparator will then use the selected reference voltage, having either a slightly higher or lower level than a nominal reference value, as the reference voltage in its operations. The difference between each level and the nominal level is the added hysteresis noise margin. The inventive mechanism uses the higher voltage level when the output of the comparator is below the nominal reference voltage, and uses the lower voltage level when the output of the comparator is above the nominal reference voltage. Thus, a noise spike in the input signal would have to be larger than the margin provided by the mechanism, before causing the comparator to react to the noise in the signal. Since the mechanism is separate from the comparator, different comparators do not have be designed and tested. The mechanism can be disabled by a shorting some of the nodes of the mechanism together during the metal layer step of the device fabrication.

On chip CMOS VLSI reference voltage with feedback for hysteresis noise margin

A method and apparatus are provided for increasing the density and performance of a Content Addressable Memory (CAM). According to one embodiment, the CAM includes a comparison circuit, an enable circuit, and a bias circuit. The comparison circuit compares a stored bit to an input bit and outputs an inverted result of the comparison. The enable circuit receives as inputs the inverted result of the comparison and an enable input and produces an enabled comparison result. The bias circuit receives the enabled comparison result as its only input and discharges a pull-down line based upon the enabled comparison result.

Increased content addressable memory (CAM) density and performance

A master-slave flip-flop and method is provided for use with critical path circuits, for example, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input inverter coupled to the pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter. The output of the driving inverter is coupled to the slave stage which includes a second pass gate through which the output of the driving inverter is applied to the master-slave flip-flop output. The above architecture results in a fast setup time and a fast clock-to-Q time without the problems associated with kickback. Also, the output of the master-slave flip-flop is tristatable.

Growing community of inventors

San Jose, CA, United States of America

Kent R Townley