Macronix International Co., Ltd.

Spansion Llc.

Kent Kuohua Chang

Fuh-Cheng Jong

Uway Tseng

Erh-Kun Lai

Jongoh Kim

Ching-Yu Chang

Tao-Cheng Lu

Hao Fang

Weng-Hsing Huang

Yider Wu

Szu-Tsun Ma

Yao-Wen Chang

Ming-Hung Chou

Wen-Pin Lu

Hung-Sui Lin

Chia-Hsing Chen

Cheng-Chen Calvin Hsueh

Nian-Kai Zous

Chao-Yang Chen

Samuel Cheng-Sheng Pan

Jen-yuan Chiu

Kenneth Wo-Wai Au

A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Method of fabricating memory

A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.

Method of fabricating multi-bit flash memory

A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfON. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.

High-K tunneling dielectric for read only memory device and fabrication method thereof

A method for fabricating a metal silicide layer includes forming a dielectric layer on a substrate, followed by forming a polysilicon material conductive layer on the dielectric layer. An adhesion layer is then formed on the conductive layer, wherein the adhesion layer is a nitrogen rich layer or a nitrogen ion implanted layer. A metal silicide layer is then formed on the adhesion layer. The adhesion between the metal silicide layer and the conductive layer is more desirable due the adhesion layer.

Method for fabricating metal silicide

A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.

Silicon nitride read-only-memory

A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (SiGe; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.

Method for fabricating locally strained channel

A fabrication method for a silicon nitride read only memory includes sequentially forming a tunneling oxide layer and a charge capture layer on a substrate. An isolation region is formed in the charge capture layer to partition the charge capture layer into a plurality of charge capture blocks. A stacked dielectric layer is then formed on the charge capture layer and the isolation region. Thereafter, the stacked dielectric layer and the charge capture layer are patterned to expose regions of the substrate for forming bit lines, followed by forming a field oxide layer and a control gate. A step of threshold voltage adjustment is subsequently performed such that the channel regions under the charge capture blocks are implanted to adjust the threshold voltages thereof

SiN ROM and method of fabricating the same

The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.

Mask ROM

A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

Method for fabricating non-volatile memory having P-type floating gate

A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfO N . An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.

A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer. In a programming operation, a portion of the gate structure close to the source region serves as an equivalent source region having an area greater than the drain region so that second bit effect is greatly reduced.

Hexagonal gate structure for radiation resistant flash memory cell

A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Memory device and method for fabricating the same

A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.

Method of boosting wafer cleaning efficiency and increasing process yield

A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.

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Taipei, Taiwan

Kent Kuohua Chang