Motorola Corporation

Other

Kent J Cooper

Scott S Roth

Wayne J Ray

James D Hayden

Bich-Yen Nguyen

Carlos A Mazure

Jung-Hui Lin

James R Carey

Howard C Kirsch

Michael P Woo

Robert J Crim

Ko-Min Chang

Bruce L Morton

Keith E Witek

Clinton C Kuo

Frank K Baker

Bernard J Roman

Craig S Lage

James R Pfiester

Prashant U Kenkare

John J Bowers

The remediation treatment creates environmentally neutral species from hydrocarbon contaminants. For soils having a low porosity, fissures are created in the site by, for example, fluid, i.e., hydraulic or pneumatic, fracturing. A catalyst is injected into the site and is permitted to diffuse through the site. An oxidizing agent is then introduced into the site to release a free radical in a Fenton-type reaction. The compounds react to release a free radical, which acts upon the contaminants to form environmentally neutral species. Diffusion of both compounds is aided by turbulence induced in the groundwater. A pH-adjusting compound is added to optimize reaction conditions. Reaction vapors are collected above ground, filtered, and vented to the atmosphere, reducing the chance for gas pressure buildup and possibly dangerous, potentially explosive conditions.

In situ water and soil remediation method and system

The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (,) is formed within the semiconductor substrate (,). A doped region (,) is then formed such that it abuts the trench sidewall (,). A portion (,) of the trench sidewall (,), abutting the doped region (,), is then exposed by forming a recess (,) within the trench isolation region (,). A conductive member (,) is then formed such that it is electrically coupled to the doped region (,) along the exposed trench sidewall, as well as along the major surface (,) of the semiconductor substrate (,), and results in the formation of a low resistance contact structure.

Contact structure and method of formation

The remediation treatment creates environmentally neutral species from hydrocarbon contaminants. A catalyst is injected into the site and is permitted to diffuse through the site. An oxidizing agent is then introduced into the site to release a free radical in a Fenton-type reaction. The compounds react to release a free radical, which acts upon the contaminants to form environmentally neutral species. Diffusion of both compounds is aided by turbulence induced in the groundwater. A pH-adjusting compound is added to optimize reaction conditions. Reaction vapors are collected above ground, filtered, and vented to the atmosphere, reducing the chance for gas pressure buildup and possibly dangerous, potentially explosive conditions.

The remediation treatment creates environmentally neutral species from hydrocarbon contaminants. A catalyst is injected into the site and is permitted to diffuse through the site. An oxidizing agent is then introduced into the site to release a free radical in a Fenton-type reaction. The compounds react to release a free radical, which acts upon the contaminants to form environmentally neutral species. Diffusion of both compounds is aided by turbulence induced in the groundwater. Reaction vapors are collected above ground, filtered, and vented to the atmosphere.

A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Static random access memory cell having a thin film transistor (TFT)

Memory cell having a plural transistor transmission gate and method of

The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

Method of making a contact structure

A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Method for forming contact to a semiconductor device

The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Static-random-access memory cell and an integrated circuit having a

Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.

Method for forming electrical isolation in an integrated circuit

Process forming an integrated circuit

A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).

Method of forming a self-aligned thin film transistor

Self-aligned thin film transistor

A method requiring only a single mask results in an isolation oxide (50) which is the same size as, instead of becoming larger than, the dimension originally defined by the lithographic system. A buffer layer (14) is formed over the substrate (12). An oxidation resistant layer (16) is formed over the buffer layer (14). The oxidation resistant layer (16) is etched and a disposable sidewall spacer (30) is formed adjacent to the sidewall of the oxidation resistant layer (28), and a trench region is defined (36). The trench region (36) is etched to form a trench. The disposable sidewall spacer (30) is removed and a conformal layer (48) of oxidizable material is deposited over the trench sidewall (40) and the trench bottom surface (38). The conformal layer (48) is then oxidized to form electrical isolation in the isolation regions (26) of the substrate (12).

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Austin, TX, United States of America

Kent J Cooper