Intel Corporation

Idea Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Cisco Technology, Inc.

Cisco Systems Inc.

Kent G Fielden

Harshvardhan P Sharangpani

Dale Calvin Morris

Tse-Yu Yeh

Hans J Mulder

Michael S Schlansker

Rajiv Gupta

Michael Paul Corwin

Judge K Arora

Manoj Khare

Mircea Poplingher

Rajesh Patil

Millind Mittal

James M Hull

Hans Mulden

James Hull

Harshvardan Sharangpani

Judge Kennedy Arora

Judge Kennedy Cisco Systems Inc Arora

A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data

Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

Methods and apparatuses for evaluation of regular expressions of arbitrary size

A load is executed speculatively as a dismissible load instruction, which does not take exceptions, and a check instruction, which is in the same format as the dismissible load, that when executed determines whether an exception should be taken on the dismissible load. In this manner, a load may be executed speculatively while ensuring that an exception occurs at the same time it would have occurred had the load been executed non-speculatively.

Method and apparatus for executing load instructions speculatively

A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Method for processing branch operations

A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.

Instruction template for efficient processing clustered branch instructions

A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage structures. When the hint information is in a first state, branch prediction information is stored in a first structure that provides single cycle access to the stored information. When the hint information is in a second state, the branch prediction information is stored in a second structure that provides slower access to the stored information.

Storing predicted branch target address in different storage according to importance hint in branch prediction instruction

A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.

Processor utilizing a template field for encoding instruction sequences

A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Instruction prefetch mechanism utilizing a branch predict instruction

A processor microarchitecture for efficient dynamic instruction scheduling and execution. The invention includes a predetermined number of independent dispatch queues. The invention also includes a cluster of execution units coupled to each dispatch queue such that the dispatch queue and the corresponding cluster of execution units forms an independent micropipeline. Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction relying on a producer instruction for an operand, and issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon. The instructions are issued from the dispatch queue to the corresponding cluster of execution units. In one embodiment, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing the producer instruction is readily available as an operand for execution of the consumer instruction.

Growing community of inventors

Sunnyvale, CA, United States of America

Kent G Fielden