Nortel Networks Corporation

Kent E Fisher

Jerry Louis Mizell

David J Lauson

Larry DeWayne Lewis

A system and method for determining link capacity utilization for High Level Data Link Control (HDLC) encoded links is presented. The links transport frames comprised of a known number of bits during a time period and the frames comprise variable length data packets and uniform length sync flags. A circuit, which aids in determining the link capacity utilization, includes a flag detector, a counter, a timeout register, and a shadow register. A sync flag count state is entered if a sync flag is detected by the flag detector. The counter is then incremented if a repeated sync flag is detected within a next data byte. When the time period expires the number of repeated sync flags are forwarded to the shadow register. A processor and the timeout register, which are coupled to the counter, respectively access the number of repeated sync flags and reset the counter. The processor then calculates the link capacity utilization.

Determining link capacity utilization for HDLC encoded links

A wireless telecommunications network includes a base station controller which includes a call control resource manager and a multi-function coding element embodied within a DSP and comprised of first, second and third coding resources, each embodied as a software module, for respectively performing D/A and A/D on voice, facsimile and data messages. When transferring messages from a mobile terminal to an MSC via the base station controller, the mobile terminal first informs the base station controller whether the message is a voice, facsimile or data message. The mobile terminal then transfers the message to the call control resource manager residing within the base station controller. Based upon the indicated message type, the call control resource manager selects, from the first, second and third coding resources, a resource for performing a D/A conversion of the message received from the mobile terminal. After the selected resource performs the D/A conversion of the received message, the call control resource manager transfers the converted message to the MSC. Conversely, when transferring messages from the MSC to a selected mobile terminal via the base station controller, the MSC informs the base station controller whether the message is a voice, facsimile or data message. The MSC then transfers the message to the call control resource manager. Based upon the indicated message type, the call control resource manager selects one of the first, second and third coding resources to perform an A/D conversion of the received message. The call control resource manager will then transfer the converted message to the selected mobile terminal.

Multi-function coding element and an associated telecommunications network

A programmable gate array (PGA) according to the present invention includes a plurality of state machine logic blocks and a plurality of error detecting logic blocks. Each state machine logic block of the plurality of state machine logic blocks produces a respective state with the plurality of state machine logic blocks in combination producing a system state. The plurality of state machine logic blocks are interconnected to execute logic programmed logic functions, such functions employed by a system within which the PGA resides. The error detecting logic blocks are interconnected to detect errors in the system state and to produce an error signal upon detection of an error in the system state. The error signal serves to reset operation of the plurality of state machine logic blocks. The plurality of state machine logic blocks may be one-hot encoded wherein, during non-error states, only one of the states produced by the plurality of state machine logic blocks is logic high. In such case, the plurality of error detecting logic blocks detects an error in the system state when more than one of the states produced by the plurality of state machine logic blocks is logic high or when none of the plurality of state machine logic blocks is in a logic high state. In producing the error signal, the plurality of error detecting logic blocks may be connected in a multi-level hierarchy.

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Rowlett, TX, United States of America

Kent E Fisher