Western Digital Technologies, Inc.

Seagate Technology Incorporated

Kent Douglas Anderson

Anantha Raman Krishnan

Shafa Dahandeh

Guangming Lu

James N Malina

Shayan Srinivasa Garani

James C Alexander

Daniel Lee Helmick

Robert L Horn

Gregory Lee Silvus

Albert H Chen

Andrew John Tomlin

Ming Jin

Mai Ghaly

Phillip Scott Haralson

Noureddine Kermiche

Galvin Chia

Yuheng Zhang

Robert W Warren, Jr

Yibo Yin

Hao Su

David W Wheelock

Aravind Raghunathan

Alvin W Tan

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Method and system for decoding data based on association of first memory location and second memory location

Soft-decision input generation for data storage systems

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

System and method for decoding iterations and dynamic scaling

The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.

Memory die layouts for failure protection in SSDs

Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

Data availability during memory inaccessibility

A data storage system includes a plurality of Data Storage Devices (DSDs). A write command is sent to each DSD of the plurality of DSDs to each store one or more erasure coded shards of an overprovisioned number of shards. The overprovisioned number of shards is generated from an erasure coding on data to provide at least a predetermined level of data reliability. Write complete indications are received for a threshold number of shards less than the overprovisioned number of shards, with each write complete indication indicating that one or more shards of the overprovisioned number of shards has been stored in a DSD. It is determined that the data has been written with at least the predetermined level of data reliability after receiving write complete indications for the threshold number of shards, but before receiving write complete indications for all of the overprovisioned number of shards.

Write latency reduction

System and method for dynamic scaling of LDPC decoder in a solid state drive

A collective latency indicator is determined that is associated with a latency in retrieving multiple erasure coded shards generated from an erasure coding on initial data. The collective latency indicator is compared to a latency limit, and a number of erasure coded shards to retrieve is adjusted based on the comparison of the collective latency indicator to the latency limit.

Read tail latency reduction

An individual latency indicator is determined for each Data Storage Device (DSD) or memory portion of a DSD storing one or more erasure coded shards generated from an erasure coding on initial data. Each individual latency indicator is associated with a latency in retrieving an erasure coded shard stored in a respective DSD or memory portion. At least one collective latency indicator is determined using determined individual latency indicators, with the at least one collective latency indicator being associated with a latency in retrieving multiple erasure coded shards. The at least one collective latency indicator is compared to a latency limit, and a subset of erasure coded shards is selected to retrieve based on the comparison of the at least one collective latency indicator to the latency limit.

In some embodiments of the present invention, a data storage device includes a controller and a memory. The data storage device further includes an LDPC encoder and decoder, with the decoder implementing a dynamic precision-rescaling technique for improving performance. In one embodiment, the technique works by rescaling the binary representations of the input log-likelihood ratios (LLRs) and messages upon activation of decoder-state-based triggers. Various triggering functions are introduced, e.g., checking if the number of output LLRs smaller than a certain limit crosses a threshold, checking if the weight of a syndrome crosses a threshold, etc. This technique offers an improvement in the performance of the decoder.

A reader failover system and method are described for a data storage system. At least two reader systems, including a first reader element and a second reader element, situated on the same head, are employed to read a magnetic storage medium. In an aspect, the head is a two-dimensional magnetic recording (TDMR) head. Control circuitry detects when the first reader system provides less than a predetermined performance or fails, and thereafter causes the second reader system, but not the first reader system, to read the magnetic storage medium. In an aspect, a buffer stores a first reader element signal until the control circuitry detects whether or not the first reader element provides less than a predetermined performance or fails. In an aspect, when a reader element fails, data recovery is performed, and all of, or a majority of, the media continues to be readable, improving the data storage system robustness.

Read failover method and apparatus for a data storage system

A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.

Growing community of inventors

Broomfield, CO, United States of America

Kent Douglas Anderson