Motorola Corporation

Freescale Semiconductor,inc.

Motorola Mobility LLC

Kent Donald Moat

Philip E May

Raymond Brooke Essick, Iv

Brian Geoffrey Lucas

James M Norris

Silviu Chiricescu

Michael Allen Schuette

Ali Saidi

William C Moyer

Raymond B Essick

Brian Jeffrey Lucas

A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to 'valid' once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to 'invalid' in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to &#x2018;valid&#x2019;. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.

Method and apparatus for nested instruction looping using implicit predicates

A method and apparatus that allocates bandwidth among wireless sensor nodes in wireless sensor groups in a wireless sensor network (WSN) is disclosed. The method may include forming a plurality of wireless sensor node groups from a plurality of wireless sensor nodes based on battery levels of the wireless senor nodes, allocating transmission time slots for the wireless sensor nodes in each of the wireless sensor node groups based on at least one channel quality metric, determining average battery levels for each of the wireless sensor node groups and average battery level of all of the wireless sensor nodes, determining differences between the average battery levels of each of the wireless sensor node groups and the average battery level of all of the wireless sensor nodes, wherein if any difference in the average battery levels is above a predetermined threshold, regrouping the plurality of wireless sensor nodes according to the battery levels of the plurality wireless sensor nodes to minimize any variance in average battery level across all of the wireless sensor node groups.

Method and apparatus for battery-aware dynamic bandwidth allocation for groups of wireless sensor nodes in a wireless sensor network

A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.

Memory address generation with non-harmonic indexing

A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor. When a specified number of data values have been produced by a particular sink, no more data values are produced by that sink. The instructions for the pipelined loop body may be repeated, without alteration, to eliminate prolog and epilog instructions.

Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters

A communication signal for transmitting a sequence of tokens over an interconnection having three wires in which each of the three wire transmits a signal corresponding to one bit of a 3-bit symbol. The tokens are determined by the transitions between the symbols. In one embodiment, RF emission is minimized and self-clocking is achieved by changing exactly one bit of a symbol at each transition. A receiver detects a transition in the signal on one of the three wires, identifies the transition from the previous and current 3-bit symbols and determines the information token associated with the transition.

Component interconnect with self-clocking data

A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. The sequence of instructions for a loop is compressed by identifying a set of aligned fields that contain NOP instructions in all of the control words of the sequence. The sequence of control words is then modified by removing the fields of the identified aligned set containing NOP instructions and adding an identifier that identifies the set of fields removed. The sequence of control words is processed by fetching the identifier at the start the loop, then, for each control word in the sequence, fetching a control word and reconstructing the corresponding uncompressed control word by inserting NOP instructions into the compressed control word as indicated by the identifier. The identifier may be a bit mask and may used to disable memory units and processing elements for the duration of the loop to reduce power consumption by the processor.

Dataflow graph compression for power reduction in a vector processor

Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Data processing system using multiple addressing modes for SIMD operations and method thereof

A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.

Queuing cache for vectors with elements in predictable order

A bus filter includes a first bus interface connected to a system bus for receiving a virtual memory address and a second interface connected to the system bus for transmitting a physical memory address. In operation, an address translation unit, such as a translation lookaside buffer, determines the physical memory address from the virtual memory address. The bus filter may be used to couple a processing device, such as an accelerator, to a system having a core processor and an external memory unit coupled by a bus.

Bus filter for memory address translation

A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

Streaming vector processor with reconfigurable interconnection switch

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Scheduler of program instructions for streaming vector processor having interconnected functional units

A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values

A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Method of programming linear graphs for streaming vector computation

An interconnection device () with a number of links (and), each link having a number of link input ports (), link output ports () and storage registers (). An input selection switch () is coupled to a selected link input port to receive an input data token. The storage registers () may be used to store input data tokens. A storage access switch () is coupled to the input selection switch () and to the storage registers () and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch () receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

Interconnection device with integrated storage

A memory interface device ( ) providing a fractional address interface between a data processor ( ) and a memory system ( ) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator ( ) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit ( ) coupled to the address generator ( ) for retrieving first and second data values from the memory system ( ) at the first and second memory addresses, respectively. The device also includes a data access unit ( ) for interpolating between the first and second data values and passing the interpolated value to the data processor ( ). The memory interface has application in a variety of data processing systems, including digital signal processors and streaming vector processors.

Growing community of inventors

Winfield, IL, United States of America

Kent Donald Moat