Broadcom Corporation

Motorola Corporation

Kent Charles Oertle

Darrin Robert Benzer

Robert Elio

Duncan McFarland

Hooman Darabi

Xiangdong Chen

Henry Kuo-Shun Chen

Jennifer Chiao

Paul Chang

Ramachandran Venkatasubramanian

Ming Wang Sze

Jia S Chiang

Duncan Mcfarland

Robert F Elio

An electrostatic discharge clamp may include a reference generator and a comparator. The electrostatic discharge clamp may be characterized by a time constant. A voltage difference caused by an electrostatic discharge event may activate the electrostatic discharge clamp. The comparator may hold the electrostatic discharge clamp in an active state responsive to a reference voltage provided by the reference generator. A duration of the active state of the electrostatic discharge clamp may facilitate dissipation of the electrostatic discharge event.

Electrostatic discharge clamp

According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.

Method for selective gate halo implantation in a semiconductor die and related structure

Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.

Method and system for mitigating risk of electrostatic discharge for a system on chip (SOC)

Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

5 volt tolerant IO scheme using low-voltage devices

Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

Method and circuit for reducing HCI stress

5 Volt tolerant IO scheme using low-voltage devices

A differential ECL signal is converted to a first current and a second current that are proportional to the ECL signal. An upper output transistor (16) and a lower output transistor (57) are selectively enabled and disabled by the first current. The second current is used to enable discharging of a storage capacitance of the lower output transistor (57) thereby substantially disabling the lower output transistor (57) before the upper output transistor (16) is enabled. In addition, a capacitor is used to momentarily discharge the storage capacitance as the upper output transistor (16) is enabled. The capacitor is discharged when the upper output transistor (16) is disabled.

Growing community of inventors

Phoenix, AZ, United States of America

Kent Charles Oertle