Loral Aerospace Corp.

Lockheed Martin Aerospace Corporation

Kent Cauble

Mark L Kenworthy

Carson Kaan

Dale D Miller

Brian T Soderberg

David Bakeman

Annette Janett

Mark N Heinen

Douglas Pheil

Dale Miller

A fuzzy logic load management controller for use with a computer image generator. The load management controller is used use with a computer image generator having a plurality of inputs and a plurality of outputs, and includes an adder that couples inputs to the image generator. The load management controller comprises a fuzzy logic controller disposed in a feedback loop between the output of the image generator and the adder. The load management controller includes a fuzzy logic inference engine, a set of membership functions coupled to the inference engine, and a rules database coupled to the inference engine that includes a set of if-then rules that specify the response of the fuzzy logic controller to inputs applied thereto. The fuzzy logic controller provides for load management of the image generator that gracefully degrades a viewed scene, keeps the image update rate constant, and renders important objects in the viewed scene.

Fuzzy logic control for computer image generator load management

An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses small sub-regions (64.times.64 pixels) and assigns many sub-regions from different channels to a single tiler. Each tiler maintains equal loading .even with localized regions of high pixel processing. The third level relates to two-by-two pixel, fixed interleave processing. The image is further divided into 2.times.2 pixel blocks spread across multiple pixel operators on a tiler. This fine grain parallelism, in a fixed pseudo-random orientation, ensures equal loading across all pixel processors. The second aspect of the present invention is the use of polygon and pixel distribution buses. Maximum image generator configurability, expansion, and efficient processing is required for a variety of simulator configurations used in networked training environments. To accomplish this, distribution buses are implemented between all graphics processing stages.

Image generator architecture employing tri-level fixed interleave

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Renton, WA, United States of America

Kent Cauble