Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Intel Corporation

Kent Andrew Dickey

James Curtis Farmer

Michael L Ziegler

Debendra Das Sharma

Ashish Gupta

Bahaa Fahim

Jonathan C Jasper

Dean T Lindsay

Robert D Snyder

Robert C Douglas

Gerald Everett

Edward M Jacobs

Karthik Ramaswamy

Kathleen C Nix

The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

Method for allowing distributed high performance coherent memory with full error containment

An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

Pass through debug port on a high speed asynchronous link

A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections&#x2014;one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.

System and method for multi processor memory testing

In a technique for testing processor interrupt logic, interrupts are sent to a microprocessor under test in a random order to test the processor interrupt logic of the microprocessor under test. The processor interrupt logic is considered to have failed the test if the microprocessor under test services a new interrupt having a priority level equal to or lower than a priority level of a previously received interrupt being serviced just prior to the receipt of the new interrupt. Furthermore, pseudo-masked interrupts are included in the interrupts being sent to the microprocessor under test. If a pseudo-masked interrupt is serviced by the microprocessor under test, the processor interrupt logic is considered to have failed the test. On the other hand, if the pseudo-masked interrupt is not serviced by the microprocessor under test, a lower (that is, soft) limit of the pseudo-masked interrupts is increased to that of the received pseudo-masked interrupt which has not been serviced by the microprocessor under test.

Technique for testing processor interrupt logic

The present invention provides for a method and system for allowing non-trusted partitions in large scale computer system to safely interrupt a processor without the risk of corruption or loss of interconnect bandwidth, and without the need for inefficient hardwiring. In operation code preferably located outside of the central processor, interrupts coming from outside the partition into specific addresses for determination of allowability into the partition.

System and method for allowing non-trusted processors to interrupt a processor safely

A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.

Circuit for allowing data return in dual-data formats

A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (&ldquo;GFC&rdquo;) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed

A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor of thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock may be run throughout the system to integrated circuits. The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock. This ensures that the event will also be seen on a rising edge of every other system clock, which makes the event appear at the same time throughout the system. By ensuring that an asynchronous function, such as a reset function, appears at the same time throughout the system, the system becomes repeatable. That is, the clock states will be the same every time an asynchronous event is released to the system.

Method for triggering an asynchronous event by creating a lowest common denominator clock

A method and apparatus for detecting, enabling and disabling deadlock errors, and recording deadlock information in the error logs of a data processing system even after a power-on reset. One embodiment of the invention involves a method for indicating a deadlock error in a data processing system capable of having a deadlock error. The method includes indicating that an error is a deadlock error, providing an input signal to set a deadlock error enable circuit having an output signal indicating that the deadlock error will cause a deadlock reset signal to be asserted, logically ORing deadlock error signals to produce a deadlock output; and logically ANDing the deadlock output and the output signal of the deadlock error enable circuit to produce the deadlock reset signal. A second embodiment of the invention involves a data processing system or an error log system, capable of having a deadlock error selected from several deadlock errors. The data processing system or error log system includes a deadlock error enable circuit having an output signal indicating that the deadlock error will cause a deadlock reset signal to be asserted, a first combinational logic circuit to logically OR the deadlock signals, having a deadlock output, and a second combinational logic circuit to logically AND the deadlock output of the first combinational logic circuit and the output signal of the deadlock error enable circuit, to produce the deadlock reset signal.

Apparatus and method for detecting, diagnosing, and handling deadlock errors

A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

System and method to protect vital memory space from non-malicious writes in a multi domain system

The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set, any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

An apparatus and method using a set of registers for indicating multiple error levels in a data processing system, recording information for each error level, and providing an order register to allow software or a user to determine the sequence order in which errors occurred. One embodiment of the invention involves a method for indicating errors in a data processing system with multiple error levels, indicating that an error corresponds to an error level, representing the error with a set of memory cells, and recording the order in which the error has occurred. A second embodiment of the invention involves a data processing system, including a primary error log to record an error, and at least one error logging register that can record information about the error. A third embodiment of the invention involves an error log system, including a primary error log to record an error having a corresponding error level, an error logging register corresponding to one of a plurality of error levels to record information about the error, and an error order register to record information about the order of occurrence of the error.

Apparatus and method for providing error ordering information and error logging information

An I/O mapping within a system memory of a computing system assigns a fixed address to each I/O device and I/O bridge in a larger address region of the system than the number of address bits of the I/O devices and/or the I/O bridges would allow. This fixed address assignment eliminates problems associated with fragmentation of I/O memory space of a conventional variable address assignment when I/O devices and/or I/O bridges are replaced on-line, i.e., hot-swapped. The I/O mapping utilizes a greater number of address bits than the address bits available from I/O devices to assign a much larger address space to each device by translating the larger number of bits address from the system to the smaller number of bits address of the I/O devices.

Method for assigning addresses to input/output devices

A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories. A mask may be used to extract portions from a logical address to index into a table mapping the logical address space onto the memories. Another portion of the logical address includes a memory offset.

Memory address interleaving and offset bits for cell interleaving of memory

A system and method is described in which protected memory writes are achieved in single transaction without leaving open a window in time for erroneous data to corrupt space in a target register. A single data packet preferably includes both user data to be written to a target storage device or location as well as the key data for authorizing the writing of such user data. Key data is preferably calculated by manipulating user data contained in the same packet or transmission thereby simplifying a verification process conducted the controller associated with target storage location.

Growing community of inventors

Westford, MA, United States of America

Kent Andrew Dickey