Mitsubishi Electric Corporation

Kensuke Taguchi

Yasuhiro Kagawa

Yoshinori Matsuno

Kazunari Nakata

Yasushi Takaki

Kosuke Miyazaki

Hiroshi Watanabe

Tomohide Terashima

Akihiro Koyama

Shiro Hino

Atsushi Narazaki

Yutaka Fukui

Rina Tanaka

Kohei Ebihara

Katsutoshi Sugawara

Nobuo Fujiwara

Ryu Kamibaba

Kotaro Kawahara

Hidenori Koketsu

Chihiro Tadokoro

Kazuya Ishibashi

Masahiro Yokogawa

Akemi Nagae

A power semiconductor device includes a termination region having a corner and an element region inside the termination region. An SiC substrate spans the element region and the termination region. An interlayer insulating film has an outer edge in the termination region. A source electrode is in contact with the SiC substrate in the element region, and has an outer edge on the interlayer insulating film in the termination region. An insulating protective film covers the outer edge of the interlayer insulating film and the outer edge of the source electrode, and has an inner edge on the source electrode. At the corner of the termination region, the outer edge of the interlayer insulating film has a radius of curvature R, and the inner edge of the insulating protective film has a radius of curvature R. The radius of curvature Ris greater than the radius of curvature R

Power semiconductor device and power converter

A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.

Method for manufacturing semiconductor device

A first electrode film is electrically connected to a source region of a semiconductor substrate, and disposed over a main surface of the semiconductor substrate. A second electrode film is electrically connected to a gate electrode, and disposed over the main surface. A third electrode film is disposed over the main surface away from the first electrode film. A protective dielectric film is disposed over the main surface, covers only a portion of each of the first electrode film and the second electrode film and covers at least portion of the third electrode film, and is made of a thermosetting resin. The main surface has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion crossing the inner region and covering at least portion of the third electrode film.

Semiconductor device and power converter

A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.

Semiconductor device and method for manufacturing semiconductor device

Even when a stress is applied due to energization or switching operation, a connection state of electrode layers can be appropriately maintained. A semiconductor device includes a semiconductor layer of first conductivity type, an upper surface structure formed on a surface layer of the semiconductor layer, and an upper surface electrode formed over the upper surface structure. The upper surface electrode includes a first electrode formed on an upper surface of the semiconductor layer, and a second electrode formed over an upper surface of the first electrode. The first concave portion is formed on the upper surface of the first electrode. A side surface of the first concave portion has a tapered shape. The second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion.

Semiconductor device and power conversion device

There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

Semiconductor device and method of manufacturing same

A drift layer contains first conductivity type impurities. A well region contains second conductivity type impurities. A source region is provided on the well region and contains the first conductivity type impurities. A well contact region is in contact with the well region, contains the second conductivity type impurities, and has an impurity concentration on the second surface higher than the impurity concentration on the second surface in the well region. A gate electrode is provided on a gate insulating film. A Schottky electrode is in contact with the drift layer. A source ohmic electrode is in contact with the source region. A resistor is in contact with the well contact region and has higher resistance per unit area than the source ohmic electrode.

Silicon carbide semiconductor device and power conversion apparatus

A silicon carbide substrate is provided with a first surface and a second surface opposite the first surface. The silicon carbide substrate includes an n-type region connecting the first surface and the second surface, and a p-type region being in contact with the first surface and connecting the first surface and the second surface. A first anode electrode is Schottky-joined, on the first surface, to the n-type region. A first cathode electrode is ohmically joined, on the second surface, to the n-type region. A second anode electrode is ohmically joined, on the first surface, to the p-type region. A second cathode electrode is Schottky-joined, on the second surface, to the p-type region.

Silicon carbide semiconductor device having high breakdown voltage and low on resistance

A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.

Semiconductor device having a gate trench and an outside trench

An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/&#x3bc;s.

Silicon carbide semiconductor device

A semiconductor device according to the present invention includes, in a termination region, a p&#x2212; type breakdown voltage holding region that is an impurity region formed in a predetermined depth direction from a substrate surface of an n&#x2212; type substrate, a first insulating film formed on the n&#x2212; type substrate so as to cover at least the p&#x2212; type breakdown voltage holding region, a first field plate formed on the first insulating film, a second insulating film formed so as to cover the first field plate and the first insulating film, and a second field plate formed on the second insulating film. The first insulating film is thicker in a corner portion than in an X-direction straight portion and a Y-direction straight portion.

Growing community of inventors

Tokyo, Japan

Kensuke Taguchi