Hitachi, Ltd.

Kensuke Ooyu

Yasuo Kurosu

Koichi Okazawa

Hitoshi Kawaguchi

Yoshihiro Yokoyama

Shigeo Tsujioka

Mitsutoshi Uchida

Kazumi Kubota

Nobuaki Izuno

A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state. When the co-processor is to perform data read/write relative to the memory, the control signal generator generates the control signal to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state, and while the first data input/output terminal is set at the high impedance state, the main processor performs read/write control of the memory bus, and the co-processor performs data transfer from/to the memory bus via the second data input/output terminal.

Data transfer control method and apparatus for co-processor system

A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.

Synchronizing circuit for an external signal and an internal sampling

Growing community of inventors

Yokohama, Japan

Kensuke Ooyu