Nec Corporation

Elpida Memory, Inc.

Other

Ps4 Luxco S.a.r.l.

Kensuke Okonogi

Kiyonori Oyu

Koji Hamada

Kiyonori Ohyu

Kenya Kobayashi

Tomohiro Hamajima

Takuo Ohashi

Kazuto Mori

Satoru Yamada

Hiroyuki Ohta

Hiroaki Kikuchi

Hirotaka Kobayashi

Kazutaka Manabe

Masaharu Watanabe

Kazuhiro Nojima

Hideharu Miyake

Tsukasa Ohoka

Kazuo Ogawa

Keiichi Watanabe

Yasushi Kozuki

Toshihiro Imamura

A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.

Semiconductor device and manufacturing method thereof

A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cmor more in the range of 0.2 to 1 &#x3bc;m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.

Semiconductor device

A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.

Method of manufacturing a semiconductor device with multilayer sidewall

A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

Semiconductor device and method of forming the same

A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Method for manufacturing a semiconductor device having polysilicon plugs

In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.

Semiconductor chip with a porous single crystal layer and manufacturing method of the same

A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.

Method for manufacturing a semiconductor device

In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2&#xd7;10(1/cm) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.

Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon

A method for manufacturing a DRAM device includes a hydrogenating step conducted to source/drain diffused regions in a hydrogen ambient at a substrate temperature not lower than 350 degrees C., and a dehydrogenating step in an inactive gas ambient at a substrate temperature of lower than 350 degrees C., before a packaging step. If a defective cell having a lower refreshing time is found in the test before the packaging step, the defective cell is replaced by a redundant cell. The resultant DRAM has a lower degradation in the refreshing characteristic after the packaging step.

Method for manufacturing a semiconductor device having a low junction leakage current

A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.

A surface of a substrate is oxidized at a temperature equal to or higher than 1050&deg; C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a density of pits existent at the surface of a substrate is equal to or less than that prior to the oxidation treatment and a depth of a pit existent there is equal to or less than 50 nm. An element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.

Fabrication process for a semiconductor device

An insulation film is formed on a first single crystal silicon substrate, e.g., a hydrogen anneal substrate, an intrinsic gettering substrate and an epitaxial substrate. Hydrogen implantation is carried out from a surface of this insulation film, thereby forming a hydrogen implantation region in the first single crystal silicon substrate. Then, by carrying out a thermal treatment at 400 to 500&deg; C., voids are formed in the hydrogen implantation region, and the first single crystal silicon substrate is cleaved therefrom. Next, the surface of the insulation film and a surface of a second single crystal silicon substrate are laminated and then, they are subjected to a thermal treatment at 1,000&deg; C. or higher. With this method, the adverse influence, on a device, of defects in the substrate can be reduced and a yield can be enhanced.

Laminated SOI substrate and producing method thereof

A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.

Growing community of inventors

Tokyo, Japan

Kensuke Okonogi