Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kensuke Odani

Taketo Heishi

Akira Tanaka

Tetsuya Tanaka

Nobuo Higaki

Shuichi Takayama

Shinya Miyaji

Hajime Ogawa

Kenichi Kawaguchi

Hirohisa Tanaka

Junko Sayama

Masato Suzuki

Yoshihiro Koga

Kiyohiko Sumida

Takaharu Morohashi

Fumio Sumi

Hiroshi Yukawa

Ryoichiro Koshimura

Shuishi Takayama

A media processing method for performing media processing by causing a processor to execute plural program modules, includes controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer. The method further includes causing the processor to perform data conversion on the media data, by executing the second program module in the second layer, the data conversion being part of the media processing.

Media processing method and media processing program

A media processing method for performing media processing by causing a processor to execute plural program modules, including: a first step of controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer; a second step of calling at least one third program module in a third layer, the third layer being lower than the second layer, by executing the second program module in the second layer; and a third step of causing the processor to perform data conversion on the media data, the data conversion being an element of the media processing, by executing the third program module in the third layer.

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1unit field in the parallel execution code, and the long instruction is assigned to the sunit field to the (s+k&#x2212;1)unit field in the same parallel execution code.

Instruction converting apparatus using parallel execution code

According to program converting step Sof the present invention, classes whose objects are created out of the classes included in a program are detected and the result is recorded in an analysis information storing sectionat an object analyzing step S, functions (unnecessary functions) regarding classes whose objects are not created are analyzed in accordance with information held in the analysis information storing sectionand the result is recorded in the analysis information storing sectionat an unnecessary function analyzing step S, and definitions of the unnecessary functions are deleted in accordance with information held in the analysis information storing sectionat an unnecessary function deleting step S

Program converting method and storage medium

PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR

Each of registers R to R is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit outputs information to the selectors and on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors and selects one out of pieces of data that have been output from first, second, and third arithmetic operation units , and and writes the selected data in the upper or lower area in one register. A dependency analysis unit in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit rearranges the instructions and generates execution codes using the dependency graph.

Processor, compiling apparatus, and compile program recorded on a recording medium

A parallel data processing system is provided for increasing the program execution rate of a target machine. A parallelizer converts intermediate code, which has been generated by a compiler front end, into a parallelly executable form. An execution order determiner determines the order of the basic blocks to be executed. An expanded basic block parallelizer subdivides the intermediate code of the basic blocks into execution units, each of which is made up of parallelly executable instructions, following the order determined and on the basic block basis. When a particular one of the basic blocks is subdivided into execution units, an instruction belonging to the first execution unit of the next basic block, which has already been subdivided into execution units, is also used.

METHOD AND SYSTEM FOR PROCESSING PROGRAM FOR PARALLEL PROCESSING PURPOSES, STORAGE MEDIUM HAVING STORED THEREON PROGRAM GETTING PROGRAM PROCESSING EXECUTED FOR PARALLEL PROCESSING PURPOSES, AND STORAGE MEDIUM HAVING STORED THEREON INSTRUCTION SET TO BE EXECUTED IN PARALLEL

An instruction string optimization apparatus is provided which estimates the size of a constant to be resolved as an address difference before linking instructions. The apparatus comprises code dividing means ( ) for dividing a serial assembler code ( ) into basic blocks, size dependence relation generation means ( ) for analyzing size dependence relations among the sizes of the instruction string between basic blocks, estimation order determining means ( ) for determining the order of basic blocks in which the size of a constant to be resolved as an address difference is determined and size determining means ( ) for determining the size of the constant in each basic block according to the determined order, whereby the size of a constant to be resolved as an address difference can be estimated to be a value close to and not less than its actual size, the number of codes can be reduced, and the process speed by a linker can be improved.

Instruction string optimization with estimation of basic block dependence relations where the first step is to remove self-dependent branching

Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions

Each of registers R to R is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit outputs information to the selectors and on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors and selects one out of pieces of data that have been output from first, second, and third arithmetic operation units and and writes the selected data in the upper or lower area in one register. A dependency analysis unit in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit rearranges the instructions and generates execution codes using the dependency graph.

A program conversion apparatus includes: the constant division unit for specifying instructions in the serial assembler code that use large constants which cannot be arranged within the operation fields of object VLIWs and for dividing the specified instructions into divided constant use instructions for storing pieces of the large constants into the specialized constant buffer of a VLIW processor and divided constant use instructions for performing operations using the stored constants; the dependence graph generation unit for generating a dependence graph based on the execution order of each instruction in the serial assembler code after the division process by the constant division unit ; and the instruction relocation unit for relocating the instructions according to the dependence graph to generate parallel assembler code.

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Kyoto, Japan

Kensuke Odani