Sony Corporation

Kensuke Fujimoto

Masahiro Shigenobu

Koji Inoue

Atsushi Fukumoto

Shunji Yoshimura

Yasuhito Tanaka

Goro Fujita

Hirofumi Todo

Hideki Mawatari

The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal Based on data arrays of a pair of binary data outputted from a 'Viterbi' decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the 'Viterbi' decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation &#x201c;input SAM values&#x201d;&#x2266;&#x201c;data value outputted from the constant generating circuit&#x201d;, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.

Reproduced signal evaluation apparatus and method, reproduction apparatus and method, and recording apparatus and method

The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal. Based on data arrays of a pair of binary data outputted from a 'Viterbi' decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the 'Viterbi' decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation &#x201c;input SAM values&#x201d;&#x2266;&#x201c;data value outputted from the constant generating circuit&#x201d;, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.

Light beams are irradiated from a head onto an optical disc including a recording layer and a reproduction (readout) layer to open, at the reproduction layer, detection window smaller than irradiation range of light beams to thereby read out recording information of the recording layer. A resolution detecting section detects resolution on tile basis of signal level of a reproduction signal reproduced from the optical disc . A signal level detecting circuit of the resolution detecting section detects signal level of a specific mark length signal corresponding to specific mark length data in the reproduction signal which has been reproduced, and a resolution calculating circuit calculates resolution on the basis of the detected signal level of specific mark length. A reproduction control circuit controls size of the detection window so that resolution from the resolution detecting section becomes close to reference value K from a reference value output circuit to thereby efficiently carry out aperture correction.

Information reproducing apparatus and information reproducing method

This invention relates to a recording medium, data transmission apparatus, data receiver, and optical disk unit, and particularly applies to a system which transmits video data and other data or records them on an optical disk in a predetermined block unit, and permits each frame to be easily and correctly located by low volumes of identification data. At least contiguous synchronization patterns or/and contiguous synchronization patterns with one synchronization pattern interleaved therebetween are assigned with unique combinations.

Recording medium, data transmission apparatus, data receiver, and optical disk unit

In a branch metric calculating circuit, using a sample value `y` input from an A/D converter and reference levels {-1, -1/2, 1/2, 1}, branch metric calculation is performed by squaring a difference between the sample value `y` and each of the reference levels and subtracting the square of the sample value `y` from the resultant value of squaring the difference. Since actual calculation is carried out for values 2y, y-3/4, -y-3/4 and -2y in this arrangement, square operation circuits can be eliminated, thereby making it possible to simplify a configuration of a Viterbi decoder.

Viterbi decoder and viterbi decoding method

An apparatus and method are provided for moving an optical head to a desired track on a disk shaped recording medium having a pair of spiral tracks. A common address is recorded on the pair of spiral tracks. The addresses of the tracks before and after the access process are compared. Based on this comparison, a judgment is made as to whether the optical head has landed on a spiral track having a common address or a track having another address after the access process.

Apparatus and method for positioning an optical head over a disk having

A storage medium reproduction apparatus for reproducing data from a storage medium for storing data which are divided into frames of a predetermined length, each of the frames comprising a synchronizing pattern. The apparatus comprises a synchronizing pattern detection circuit for detecting synchronizing patterns and a frame determination circuit for determining a currently reproduced frame on the basis of regularity of the synchronizing patterns detected by the synchronizing pattern detection circuit.

Error-correcting storage medium reproduction apparatus and method using

An apparatus and method are provided for locating a desired track on a disk shaped recording medium. The disk has a first pre-group and a second pre-group. At least one of the pre-groups has encoded address information shared by at least one track on the inner side of the pre-group, and shared by at least one track on an outer side of the pre-group. A desired track is located based on changes in address information detected during or after a track jump.

To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9.times.Si-9.times.Si+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.

Playback apparatus and playback method

A simple device and method for accessing a desired track of an optical disk device or the like, wherein address information is encoded on at least one of two pre-groups. One or more tracks adjacent to the pre-groups have the same address. Tracks are located and identified based on changes in address information detected during or after a track jump.

Apparatus and method for identifying and accessing a desired track of an

An ECC encoder adds sync patterns to a preamble part and a data part in respectively different sequences. A modulator modulates data to which sync patterns have been added by the ECC encoder, and the result is recorded on an optical disk. The playback RF signal output by the optical disk is demodulated by a demodulator, and the sync patterns inserted in the signal are detected. From the combinations of detected sync patterns, the demodulator 12 identifies whether a currently reproduced frame is the preamble part or the data part, and from the identification result, playback data is sequentially stored in a predetermined area of a SRAM. It is thus performed to identify a preamble part from a reproduced RF signal, and accurately extract one block of data.

Recording medium, recording medium playback device, recording medium

An A/D converter supplies an interpolation circuit with sampled values which are obtained by sampling a playback signal coming from a read-out device in synchronization with a system clock signal. In the interpolation circuit, the value of the playback signal at the time the phase of a PLL clock phase signal P supplied by a PLL clockphase signal generator becomes zero is computed from the sampled values by using a linear interpolation technique. The interpolation value is then supplied to a binary conversion circuit and fed back to a phase error detecting circuit. The binary conversion circuit converts the interpolation value of the playback signal into a binary value which is then supplied to a circuit at the following stage. The phase error detecting circuit detects a zero cross of the interpolation value of the playback signal. The zero cross timing is then used for computing a phase error signal which is then output to the PLL clock phase signal generator by way of a loop filter. The PLL clock phase signal generator generates the PLL clock phase signal P which is supplied to the interpolation circuit as described above.

An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

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Kanagawa, Japan

Kensuke Fujimoto