Texas Instruments Corporation

Senju Metal Industry Co., Ltd.

Kensho Murata

Mutsumi Masumoto

Kenji Masumoto

Hiroshi Okada

Minoru Ueshima

Masazumi Amagai

Yoshitaka Toyoda

Tsukasa Ohnishi

Masako Watanabe

Takahiro Roppongi

Makoto Yoshino

Kazuaki Ano

Osamu Munekata

Daisuke Souma

Takeshi Tashima

Kunio Sakamoto

A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.

Lead-free solder

A lead-free solder alloy comprises 1.0&#x2013;5.0 wt % Ag, 0.01&#x2013;0.5 wt % Ni, one or both of (a) 0.001&#x2013;0.05 wt % Co and (b) at least one of P, Ge, and Ga in a total amount of 0.001&#x2013;0.05 wt %, and a remainder of Sn. The solder can form solder bumps which have a high bonding strength and which do not undergo yellowing after soldering.

Lead-free solder alloy

A semiconductor device designed to reduce the warp of a substrate due to curing contraction, etc. of an insulation pattern while forming the insulation pattern on the surface of a substrate so that it may be interposed between a semiconductor chip and a conductor pattern by offering a semiconductor chip mounting substrate equipped with a flexible substrate(insulating film) having a chip mounting regionfor mounting a semiconductor chipvia an adhesive, conductor patternsthat are formed on the surface of the above-mentioned substrateand electrically connected to the semiconductor chipin an external region of the above-mentioned chip mounting region, and an insulation patternformed on the surface of the substrateand partially in the chip mounting regionso that it may be interposed between the semiconductor chipand the conductor patterns

Semiconductor chip mounting substrate and semiconductor device using it

Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring () for the purpose of electrically connecting each electrode pad () and external connecting terminals on top of a wafer () on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin () such that the upper portion of the conductive supporting posts () are exposed. In a later process, solder balls () are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Semiconductor device and its manufacturing method

Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring ( ) for the purpose of electrically connecting each electrode pad ( ) and external connecting terminals on top of a wafer ( ) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin ( ) such that the upper portion of the conductive supporting posts ( ) are exposed. In a later process, solder balls ( ) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

To completely suppress or minimize the voids formed between the insulating substrate and the IC chip in order to prevent the problems of separation and cracking of the chip caused by the aforementioned voids. The present invention is preferably adopted for the Chip Six Package type package or other package types equipped with solder bumps or other external connecting terminals directly beneath the IC chip. For insulating substrate (3), on its chip-carrying surface, there is pattern element (6) in the region beneath the IC chip and free of conductor pattern elements (4) in addition to conductor pattern element (4) for forming electrical connection between the electrode pads and the external connecting terminals of the chip. Said pattern element (6) divides said region into plural small regions A. IC chip (2) is bonded through die paste on insulating substrate (3) such that an end of conductor pattern element (4), pattern element (6) and divided small regions A are covered. Pattern element (6) acts to reduce the shifting of die paste (9) before curing due to the surface tension. As a result, the formation of voids beneath the chip can be completely prevented or minimized.

Growing community of inventors

Beppu, Japan

Kensho Murata