Kabushiki Kaisha Toshiba

Kenshi Tsuchiya

Hirofumi Kato

Masaki Miyatake

Hoko Hirai

Hiroyoshi Murata

Seiichi Sagi

A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd,is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd,through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd,through Ckdn. The output circuit outputs one of the correction subject signal Ckd,and the delayed signals Ckd,trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.

Jitter correction circuit and a flat panel display device using the same

A multi-gradation liquid crystal display having dual display definition modes that can display both TV pictures and office automation images, both without flicker. Scanning electrodes extend in a first direction. Scanning and non-scanning voltages are selectively applied to the scanning electrodes. Signal electrodes extend in a second direction perpendicular to the first direction. First and second signal voltages are selectively applied to the signal electrodes. A layer of liquid crystal is sandwiched between the scanning and signal electrodes. Mode switching is provided for switching display between a first mode wherein an image is displayed by two-gradation pixels and a second mode wherein an image is displayed by three or more gradation pixels.

Growing community of inventors

Hyogo-ken, Japan

Kenshi Tsuchiya