Axis Ab

Kenny Ranerup

Jan Bengtsson

Per Zander

Mikael Nilsson

Stefan Sandstr&ouml;m

Hans-Peter Nilsson

Ronny Ranerup

Jonas Oxenholt

The present invention relates to a computer chip having integrated thereon a CPU, and a cache system being interconnected, and at least one synchronization unit. The chip is setable in one of at least two different running modes, a first one thereof being a DUT mode, and a second one thereof being a MONITOR mode. The MONITOR mode is complementary to the DUT mode. The chip additionally comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips being in complementary modes. Said signals comprises synchronization signals generated by said synchronization unit. The present invention further relates to a computer apparatus, and a debugging system both employing at least one such chip.

Chip with debug capability

Application specific integrated circuit and transceiver with multi-mode connection

Integrated circuit and method for bringing an integrated circuit to execute instructions

An on-chip i/o-processor for controlling and communication with peripheral devices, wherein an i/o processor core (,), comprising at least one pin controller (,) for reading and setting physical i/o-pins (,), starting timers and generating interrupts for the i/o processor core (,), at least one timer (,) for sampling i/o-pins (,), setting i/o-pins (,) and generating interrupts for the i/o-processor core (,) at well defined points of time, said i/o-processor core (,) providing instructions for controlling said at least one pin controller (,), said at least one timer (,) and i/o-pins (,), an on chip RAM (,) holding instructions for the i/o processor core (,), at least one register (,) for exchanging information between the i/o-processor (,) and a connected CPU (,) on the same chip and inversely, configurable logic (,), connected between said core (,) and said i/o-pins (,), for synchronization of incoming and/or outgoing signals.

On-chip i/o processor supporting different protocols having on-chip controller for reading and setting pins, starting timers, and generating interrupts at well defined points of time

Growing community of inventors

Lund, Sweden

Kenny Ranerup