Intel Corporation

Weitek Corporation

Kenneth Y Ng

A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs select Booth-multiply functions. The circuit also includes a plurality of multiplexer circuits, one multiplexer circuit for each bit of the multiplicand. The at least one of the plurality multiplexer circuits includes four pass gates coupled to receive a multiplicand bit, a complement of the multiplicand bit, multiplexed data from a next lower order multiplexer circuit and the encoded outputs of the Booth encoder circuit outputs to provide one bit of a partial product at a multiplexer output.

Smaller and lower power static mux circuitry in generating multiplier partial product signals

An integrated circuit and method for rounding a number in one of a first or second format to produce a rounded result wherein the number is represented by a set of bits. A first incrementer increments a first subset of the set of bits in response to being enabled and a second incrementer coupled to the first incrementer increments a second subset of the set of bits in response to being enabled. Mode selection logic coupled to the first and second incrementers selectively enables one of the first or second incrementers in response to a control signal indicating the format of the number to be rounded, the first incrementer being enabled if the number is in the first format and the second incrementer being enabled if the number is in the second format.

Method and apparatus for performing floating-point rounding operations

A leading zero predictor (LZP) in parallel with the full subtraction operation correctly predicts the exact number of leading zeros of a subtraction result. Once the full subtraction operation is completed, the necessary shifts may be performed immediately, without a delay to determine the presence of leading zeros, and without need for a normalization corrector.

Method and apparatus for exact leading zero prediction for a

A method and apparatus for improving the speed of a floating-point arithmetic logic unit (ALU) by arranging the logic to provide two parallel paths, each performing four functions. Six different functions are performed, and thus there is a duplication of two functions. However, each path requires only four functions, thus reducing the throughput from six to four functions. Logic circuitry is provided to determine whether the exponents of the operands are close or not, and thus select one or the other of the two paths. The fractions of the operand are processed on the two paths in parallel while the logic is determining which path to select. This determination can thus be done in parallel, with the selection being done by a multiplexer at the end of the two parallel paths.

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Saratoga, CA, United States of America

Kenneth Y Ng