Snowbush Inc.

Other

Silsym, Inc.

Kenneth William Martin

Yunzhi Dong

David J Cassan

Mehrdad Ramezani

Jonathan E Rogers

Tony Pialis

An optical receiver including a photo detector for converting a light signal into an electrical current signal and a preamplifier circuit for receiving the electrical current signal and outputting a corresponding voltage signal. In one example, the preamplifier circuit includes a first transistor having: (i) a high impedance node connected to an input node connected to receive the electrical current signal from the photo detector, and (ii) a control terminal connected to receive active negative feedback proportional to the electrical current signal received at the input node.

Optical receiver

A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; and a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained. The circuit can be implemented in a receive path of a serializer/deserializer.

Serializer deserializer circuits

A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.

System and method for jitter control

A bias circuit for obtaining accurate on-chip time constants and resistances. The bias circuit includes a constant-g.sub.m bias circuit and feedback loop circuit. The constant-g.sub.m bias circuit has a mos transistor device and a variable resistor device which are arranged so that the trandsconductance of the transistor device is dependent upon the resistance of the resistor device. The constant-g.sub.m bias circuit generates a bias output signal that is a function of the trandsconductance of the transistor device. The feedback loop circuit includes signal generation means responsive to the bias output signal for generating a signal that is a function of the bias signal. The loop circuit further includes a comparison means for comparing the generated signal to a known external frequency reference, and an output that is operatively connected to the variable resistor device for adjusting the value of the variable resistor device until the generated signal matches the external reference signal. Also provided is a variable resistor device for use in a loop circuit (including the present bias circuit). The resistor device includes an analog-controlled resistor device and a digitally-controlled resistor device. The analog-controlled resistor device is adjusted in response to variations occurring in a control signal between a maximum voltage and a minimal voltage. The digitally-controlled resistor is adjusted in discrete steps whenever the control voltage reaches the maximum or minimum voltage, after which the control voltage is forced to a value approximately half-way between the minimum and maximum voltage.

Growing community of inventors

Toronto, Canada

Kenneth William Martin