Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Kenneth William Ferguson

Gershom Birk

Andrew S Wright

Philip Lyon Northcott

Jurgen Hissen

Brian D Gerson

Kenneth David Wagner

Chris Siu

Bradley Burke

Steven Yu Peng Ng

Paul Laprise

Michel Duchesneau

Kevin L Rodger

Kevin Chun Yeung Hung

Aaron John Dennis

Jeremy Paul James Benson

Lisa Ann Desandoli

The present disclosure provides systems and methods for testing an integrated circuit or device under test (DUT). A DUT of the present invention has a plurality of scan chains, a plurality of shift register elements each associated with a respective one of the scan chains, and a programmable switch matrix to configure shift register elements of a subset of the plurality of shift register elements to cause one shift register element of the subset to receive an interleaved test sequence, and to cause the interleaved test sequence to be shifted to other shift register elements in the subset, and to input deinterleaved test sequences to scan chains associated with the subset.

Reconfigurable scan chain connectivity to enable flexible device I/O utilization

A relatively high-speed serial data transmitter incorporates built in self test (BIST). The BIST circuit advantageously provides tests modes to obviate the need to build expensive test equipment for high-speed serial data devices, such as a serializer/deserializer (SerDes) or other transceivers. Multiple data paths in a finite impulse response (FIR) filter of transmitter of the SerDes or a transceiver can be independently tested. The transmitter output can also be selectively degraded to test a receiver of a transceiver. An attenuated output signal can be provided to test receiver sensitivity. A low-pass filter can be invoked to emulate a backplane, while a loopback circuit can provide the emulated backplane attenuation to the receiver to permit testing of the equalization circuitry of a receiver without requiring the presence of an actual backplane for testing.

Built in self test (BIST) for high-speed serial transceivers

Methods and apparatus sort integrated circuits by maximum operating speed (f). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for example, the set of all critical timing paths. For example, the timing can be generated by using static timing analysis (STA). The timing for a second set of critical timing paths is statistically characterized. The second set can be, for example, a sample set of critical timing paths that are measurable or are measured for a device during test. The timing can be based on STA, derived from a known good device, and the like. A device under test (DUT) is tested, and the timing for the second set of critical timing paths is determined. A fitting technique is used to fit the expected device characteristics and the measured data for the DUT, and in one embodiment, the parameters used for fitting are applied to the first set of critical timing paths, which are then used to determine an appropriate ffor the DUT.

Systems and methods for speed binning of integrated circuits

A test method allows testing of source-synchronous high-speed wide busses on automatic testing equipment for at-speed characterization and production at-speed testing. An integrated circuit that is verified using the method and systems including such an integrated circuit are also disclosed. The invention can enable sampling or testing of signals or test pins that that are running very fast, particular compared to available automatic testing equipment for testing these device. The invention uses data recovery emulation on various types of automated test equipment to capture output data for further, more sophisticated analysis.

Apparatus and method for high speed sampling or testing of data signals using automated testing equipment

Systems and methods for analyzing the jitter content of an oversampled digital communication signal are disclosed. Advantageously, the communication signal can correspond to an arbitrary data sequence, rather than only to a repeating test sequence. For example, the systems and methods can be embodied in test equipment and in simulation equipment as design tools and/or validation tools. The systems and methods disclosed advantageously facilitate the decomposition and quantification of the main jitter components (random and deterministic), as well as its various subcomponents (periodic jitter, data-dependent jitter, inter-symbol interference, device-state-dependent jitter, other bounded uncorrelated jitter, and data-dependent-random jitter).

Systems and methods for jitter analysis of digital signals

A loopback circuit for testing low and high frequency operation of integrated circuit transmitter and receiver components. First and second resistors forming a first branch of the circuit are series-connected between first and second circuit ports. Third and fourth resistors forming a second branch of the circuit are series-connected between third and fourth circuit ports. A DC isolator is connected between the first and second branches. At lower frequencies, the two branches are DC-isolated, enabling ATE-measurement of the transmitter's output drive level independently of the receiver, continuity testing of ESD protection structures, etc. At higher frequencies, the transmitter's output signal is split into three portions, each of which is attenuated by a selected amount. One of the attenuated signal portions is applied to the receiver to test the receiver's sensitivity, independently of possible excess resiliency in the transmitter's output drive level.

High speed I-O loopback testing with low speed DC test capability

Test device (DUT) current flow is mirrored through a capacitor. If the mirrored current is switched to bypass the capacitor, the capacitor discharges. Otherwise, the mirrored current charges the capacitor. The charging capacitor's voltage rise time is proportional to the DUT's IDDQ current. Several IDDQ reference values can be derived, each representing quiescent state operation of a defect-free copy of the DUT. An IDDQ test value is derived for each IDDQ reference value. Each test value represents quiescent state operation of the DUT after application of the test vector which produced the corresponding reference value. The reference values are compared to their corresponding test values and a plurality of scaling factors derived. Each scaling factor represents a proportionality between corresponding reference and test values. The DUT is &ldquo;non-defective&rdquo; if the scaling factors are equal within a predefined error range . Otherwise, the DUT is &ldquo;defective&rdquo;.

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Burnaby, Canada

Kenneth William Ferguson