Amazon Technologies, Inc.

Kenneth Wayne Patton

Ron Diamant

Sundeep Amirineni

Mohammad El-Shabani

Bijendra Singh

Anand Narayan Acharya

Himabindu Sajja

Randy Renfu Huang

Sagar Sonar

Willis Wang

Thomas Elmer

In one example, an integrated circuit comprises: a memory configured to store a first mapping between a first opcode and first control information and a second mapping between the first opcode and second control information; a processing engine configured to perform processing operations based on the control information; and a controller configured to: at a first time, provide the first opcode to the memory to, based on the first mapping stored in the memory, fetch the first control information for the processing engine, to enable the processing engine to perform a first processing operation based on the first control information; and at a second time, provide the first opcode to the memory to, based on the second mapping stored in the memory, fetch the second control information for the processing engine, to enable the processing engine to perform a second processing operation based on the second control information.

Hardware engine with configurable instructions

Methods and systems for performing hardware approximation of function are provided. In one example, a system comprises a controller, configurable arithmetic circuits, and a mapping table. The mapping table stores a first set of function parameters in a first mode of operation and stores a second set of function parameters in a second mode of operation. Depending on the mode of operation, the controller may configure the arithmetic circuits to compute a first approximation result of a function at an input value based on the first set of function parameters, or to compute a second approximation result of the function at the input value based on the second set of function parameters and to perform post-processing, such as quantization, of the second approximation result.

Configurable function approximation based on switching mapping table content

Methods and systems for performing hardware computations of mathematical functions are provided. In one example, a system comprises a mapping table that maps each base value of a plurality of base values to parameters related to a mathematical function; a selection module configured to select, based on an input value, a first base value and first parameters mapped to the first base value in the mapping table; and arithmetic circuits configured to: receive, from the mapping table, the first base value and the first plurality of parameters; and compute, based on a relationship between the input value and the first base value, and based on the first parameters, an estimated output value of the mathematical function for the input value.

Hardware implementation of mathematical functions

A reconfigurable processing circuit and system are provided. The system allows a user to program machine-level instructions in order to reconfigure the way the circuit behaves, including by adding new operations. The system can include a profile access content-addressable memory (CAM) configured to receive an execution step value from a step counter. The execution step value can be incremented and/or reset by a step management logic. The profile access CAM can select an entry of a profile table based on an opcode and the execution step value, and the processing engine can execute microcode based on the selected entry of the profile table. The profile access CAM can translate the opcode to an internal short instruction identifier in order to select the entry of the profile table. The system can further include an instruction decoding module configured to merge multiple instruction fields into a single effective instruction field.

Systems, methods, apparatus and computer readable medium is disclosed for extending the Virtual Routing and Forwarding (VRF) in the network using embedded source identifiers in the packets. An example apparatus may include ports, memory and processing logic. The memory may include VRF routing tables corresponding to respective VRF domains and a list of media access control (MAC) addresses, wherein each MAC address in the list is linked to one of the respective VRF routing tables. The processing logic may be configured to receive an ingress packet at a port, identify a matching MAC address in the list that matches a source identifier of the ingress packet, and process the ingress packet according to the respective VRF domain associated with the matching MAC address that matches the source identifier.

Extending virtual routing and forwarding using source identifiers

Systems, methods, apparatus and computer readable medium are disclosed for extending Virtual Routing and Forwarding (VRF) for a network. An example apparatus includes ports, memory and processing logic. The memory includes VRF routing tables corresponding to respective VRF domains. The memory may also include a list of media access control (MAC) addresses, wherein each MAC address in the list is linked to one of the respective VRF domains. The processing logic may be coupled to access the memory and coupled to the ports. The processing logic may be configured to receive an ingress packet at a port of the apparatus, identify a VRF domain that the ingress packet belongs to, process the ingress packet according to the VRF domain, and optionally generate an egress packet, by embedding/writing a MAC address in the egress packet that acts as a source identifier for the respective VRF domain.

Growing community of inventors

Bee Cave, TX, United States of America

Kenneth Wayne Patton