International Rectifier Corporation

Kenneth Wagers

Daniel Marvin Kinzer

Zhijun Qu

Ming Zhou

Jianjun Cao

Yanping Ma

The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Dual epitaxial layer for high voltage vertical conduction power MOSFET devices

A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Superjunction device and process for its manufacture

Guard ring diffusions in the termination of a MOSgated device are laterally spaced from one another and are disposed beneath and are insulated from the termination field plate which extends from the periphery of the device active area.

MOSgated device termination with guard rings under field plate

A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

Termination structure for semiconductor devices and process for manufacture thereof

A semiconductor device includes a guard ring in the termination area that is formed using the same processing steps that form the active area of the device and without requiring additional masking steps or a passivation layer. The guard ring is formed in an opening in the field oxide located in the termination area and is electrically connected to a polysilicon field plate that is located atop a portion of the field oxide region. The guard ring increases the rated voltage of the device without the introduction of a passivation layer.

Guard ring structure for semiconductor devices and process for

A method is presented for forming a guard ring of a semiconductor device in the termination area in tandem with forming the active area structure of the device. The guard ring is formed using the same processing steps that form the active region structure, at the same time, without requiring additional masking steps or a passivation layer. The guard ring is formed in an opening in the field oxide located in the termination area and is electrically connected to a polysilicon field plate that is located atop a portion of the field oxide region. The guard ring increases the rated voltage of the device without the introduction of a passivation layer.

Growing community of inventors

Los Angeles, CA, United States of America

Kenneth Wagers