Western Digital Corporation

Kenneth W Ouyang

Karl M Lofgren

Gerald W Shearer

Melvin L Marmet

Timothy G O'Shaughnessy

Alan Y Lee

Richard William Hull

Ramon Co

Kwok Fai Lee

Michael R Spaur

Kowk Fai Lee

Victor G Pierotti

David K Chung

Joseph A Souza

Jui C Liang

An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

Electro-static discharge protection circuit with bimodal resistance

An integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET). When an ESD induced voltage at an input or output node reaches the turn-on voltage determined by the zener diode breakdown voltage, the shunting transistor is turned on by current capacitively coupled to the base of the parasitic bipolar transistor inherently formed in the thick oxide FET. The parasitic bipolar transistor is turned on in its saturated mode, substantially shorting the node to ground. At the end of the ESD event when the ESD induced current is no longer sufficient to keep the shunting transistor in its saturated mode, the shunting transistor turns off and the ESD protection circuit returns to its off mode, monitoring the input or output node for the occurrence of another ESD event.

Capacitively induced electrostatic discharge protection circuit

A field effect transistor device formed on an integrated circuit chip substrate and driven by the on-chip voltages having a well region formed in the substrate, and source and drain regions one of which is formed in the well region. The well region has a lower doping concentration than the source and drain regions and is of the same conductivity type. The well region provides a reduced electric field gradient at the source/substrate or drain/substrate junction and significantly increases the breakdown resistance of the device to DC voltages higher than the on-chip voltages. An input/output protection circuit employing the field effect transistor coupled in series between an integrated circuit output pad and the active devices on the chip providing ability to withstand coupling of the pad to a relatively high DC voltages.

High DC breakdown voltage field effect transistor and integrated circuit

A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage. A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

Variable frequency system having linear combination of charge pump and

An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects. In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise. A dynamic clamp suppresses voltage spikes extending outside the voltage supply operating range. A bias circuit arrangement compensates for sheet resistivity of the integrated circuit chip. If the resistance value of the sheet drops below a prescribed value, the fixed current is limited so it cannot exceed its designed value.

Method and apparatus for reducing transient noise in integrated circuits

A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.

Phase-locked loop delay line

An integrated circuit chip is fabricated with an operational active device and a nearly-identical, exemplary active device. The exemplary device is connected in series with a current reference element so that current flow through the reference element will be substantially duplicated in the exemplary device. A difference amplifier senses the output voltage of the exemplary device; compares it to a provided reference voltage; and generates a gate biasing level at the gate of the exemplary device to force the output voltage of the exemplary device substantially equal to the reference voltage. The biasing level at the gate of the exemplary device is duplicated at the gate of the operational device thereby creating a condition wherein the output current of the operational device will be a substantially precise replica of the current flow through the reference element when the reference voltage is duplicated across the output of the operational device.

Biasing circuit for generating precise currents in an integrated circuit

A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.

CMOS integrated circuit having precision resistor elements

A charge pump implemented in a CMOS monolithic circuit provides a precise output charging current source or current sink with fast switching characteristics. Each of two CMOS output transistors is connected via a transmission gate to a transistor having a constant current flow through it. An MOS capacitor is connected to the gates of the constant current transistors. When a transmission gate is closed, the respective output transistor is coupled to the constant current transistor in a current mirror configuration. The output transistor is quickly switched on to cause a step change in output current.

Fast switching charge pump

The present invention provides an apparatus and method for allowing an electronic device to drive large values of load capacitance without generating high levels of transient noise. Means are provided for passing a first current through the parasitic inductance of the integrated circuit prior to the activation of the output driver, presoaking the parasitic inductance. Thereafter, when the output driver is activated and the load capacitance discharges through the inductance of the integrated circuit, the first current is removed from as the current from the load capacitor replaces it. Since an initial level of current existed through the inductance, the rate of change of current passing through the inductance during activation of the output driver is maintained approximately constant, thereby reducing the level of transient noise generated by the electronic device.

Method and apparatus for reducing transient noise by premagnetization of

A CMOS Schmitt Trigger circuit includes a differential structure for comparing an input signal with a feedback signal and a feedback circuit for providing the feedback signal with one of two voltage levels. A CMOS switch pair is connected to one or both of the differential structure and feedback circuit to provide power to the circuit only when necessary so as to minimize power consumption.

Low current high precision CMOS schmitt trigger circuit

A power-up reset circuit for providing a reset signal for resetting circuit elements such as flip-flops upon the application of power to the circuit includes a CMOS pair output section and a capacitor coupled to the gates of the CMOS transistors. The capacitor is charged up by the power supply to switch the reset signal to a low level after the resetting operation has been achieved. In order to accommodate slow ramping power supplies, circuitry operating as a voltage sensitive switch is included to prevent the capacitor from charging until the power supply voltage has reached a sufficient level to ensure proper operation. In order to accommodate fast ramping power supplies, the charging rate of the capacitor is controlled to assure a minimum necessary duration of the reset signal.

Voltage level sensing power-up reset circuit

A voltage controlled oscillator includes an inverting amplifier connected to a resonant feedback network and a comparator for comparing the input to the inverting amplifier to a reference voltage which is equal to the threshold voltage of the inverting amplifier. As a result, the oscillator provides a square wave output having a precise one-to-one duty cycle. In addition, circuitry is included for causing the oscillator to start up at a steady state value and predetermined phase.

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Huntington Beach, CA, United States of America

Kenneth W Ouyang