Burr-brown Corporation

Texas Instruments Tucson Corporation

Texas Instruments Corporation

Kenneth W Murray

Joel Martin Halbert

Dan Yuan

An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide &ldquo;pole-zero&rdquo; compensation to the output stage amplifier circuit.

Output stage amplifier with compensation circuitry

A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Method for bias rail buffering

Bias rail buffer circuit and method

A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.

Current mirror circuit

A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

Wideband operational amplifier

A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an NPN cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

Compensation circuit for input stage of high speed operational amplifier

A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. Low gain amplification circuit transistors are located adjacent to the low gain differential input circuit and disposed along the thermal centerline between the low gain differential input circuit and the output drive circuit stage to provide approximately balanced response to the low gain amplification circuit transistors to differential heating by the output driver circuit. Compensated bias current circuitry is located along the fourth edge and adjacent to the low gain amplification circuit transistors and the output driver circuit.

Topography for integrated circuit operational amplifier

A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit. The bonding pads, which function as heat sinks, also are symmetrically disposed on or about the thermal centerline.

Growing community of inventors

Tucson, AZ, United States of America

Kenneth W Murray