U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Kenneth W Moulding

John B Hughes

Gordon A Wilson

David W Parker

Jonathan R Canning, Deceased

In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is formed as two or more sub-transistors, the channel length of one sub-transistor being unequal to that of the other(s).

MOS transistor having first and second channel segments with different widths and lengths

Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the 'on' resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.

Switched current circuits

A current memory comprises an input which is connected via a switch which is closed on a phase .phi.1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell(M2). The coarse memory cell samples the input current on phase .phi.1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory on phase .phi.1b of the clock. A second switch which is closed on phase .phi.2 of the clock passes the combined outputs of the coarse and fine memories to an output. Two further switches are provided which are closed for a short time (sh1) at the start of phase .phi.1b. The two further switches discharge the stray capacitance (C.sub.n) at the node (2) to the voltage reference source via a terminal.

Current memory

A current memory has an input (1) which is connected via a switch (S1) to inputs of a coarse memory cell (CM) and a fine memory cell (FM). On a phase .phi.1 of a clock signal the switch (S1) closes. During a first part .phi.1a of the clock .phi.1 of the coarse memory cell samples the input current and the outputs the sampled current thereafter. During a second part .phi.1b of the clock .phi.1 the fine memory cells senses and stores the difference between the input current and the output current of the coarse memory (CM). An output switch (S5) closes on phase .phi.2 of the clock, thereby passing the combined outputs of the coarse and fine memories to an output (2). A resistor r.sub.s is provided between the common nodes of the coarse and fine memories, having a resistance equal to the 'on' resistance of the output switch (S5). This substantially compensates for the voltage drop caused by the internal resistance of the output switch in the closed state, thereby reducing current transport error between the coarse and fine memories.

Analog current memory having resistance to reduce current transport error

A switched current differentiator includes first and second interconnected current memory cells, An input current is applied to terminal (1) and is fed on line (2) to the current memory cells, A first output current is derived from the first current memory cell via a transistor and a second output current is derived from the second current memory cell via another transistor. The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output via a switch on odd phases of a clock signal and is fed directly to the output via a further switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feeback loop. In a fully differential version of the differentiator the inverters may be constructed by the correct interconnection of the differential signals, i.e. by crossing over connections.

Switched current differentiator

A current memory for balanced current inputs comprises two coarse and two fine current memory cells each of which comprises a field effect transistor having a switch between its gate and source electrodes. Parasitic gate-drain capacitances are neutralised by capacitors connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors.

A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which, during a first phase of a clock cycle, an input current is fed to the inputs of the current memory cells and during a second phase of the clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2). A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell and an inverted, scaled version of the current stored in the first memoy cell.

Switched-current bilinear integrator sampling input current on both

An analogue current memory arrangement includes an input (30) and an output (33). A first (coarse) current memory cell (T31,S31,C31) senses the input current during clock phase .phi.1a and reproduces the sensed current during clock phases .phi.1b and .phi.2. A second (fine) current memory cell (T32,C32,S32) acts as a current source during phase .phi.1a when a reference voltage (VR) is applied to the gate of transistor (T32). The second current memory cell senses the difference between the input current and the output of the first current memry cell during phase .phi.1b and reproduces the sensed current during phase .phi.2. During phase .phi.2 the input switch (S30) is opened and the output switch (S34) is closed causing the combined outputs of the first and second current memory cells to be fed to the output (33). (FIGS. 3 and 4).

Analog current memory

Switched current circuits include current memory cells which store analogue currents by way of the charge on the gate source capacitance of an MOS transistor. A source of inaccuracy in these circuits is switch charge injection into the gate source capacitance. It has been found that the error current produced by a single current memory cell is relatively flat over a current range centered above a peak value of stored current. When two current memory cells are connected in cascade this error may be cancelled. In order to produce equal errors an optimum bias current is generated which depends on parameters variable in integrated circuit manufacturing processes but which are relatively constant within an individual integrated circuit. The two cascaded current memory cells include controllable bias current sources and a control circuit controls the current sources so that the current memory cells operate at the optimum bias current. The control circuit includes two further current memory cells connected in cascade and two different value current sources are provide. The error current due to switch charge injection charges a capacitor (Cx). The voltage across this capacitor controls current sources (T16,T17) and also current sources (T14, T15). The current sources (T14,T15) and capacitor form a control feedback loop that causes the bias current to approximate the optimum value.

Signal processing arrangements

In an integrated circuit in which the capacitances of a pair of capacitors are arranged to be in a ratio k by choosing the areas of corresponding plates of the two capacitors to be in this ratio, and the plates are shaped so that the total lengths of their boundaries are also in this ratio so as to reduce the sensitivity of k to manufacturing tolerances, this sensitivity is further reduced by arranging that the ratios between the numbers of 90.degree. corners exhibited by the respective plates, and the numbers of 270.degree. corners exhibited by the respective plates, are each also substantially equal to k. To make this possible an aperture is arranged to be present in each plate.

Ratioed capacitances in integrated circuits

An integrated temperature threshold sensing circuit comprises first and second bipolar transistors (Q1, Q2) biased so that the current density in the first transistor is larger than that in the second transistor by a first known factor. The first and second transistors have their collectors and bases connected to a first bias voltage source and to a second bias voltage source, respectively, and their emitters connected respectively to first and second current sources (12,14) for passing first and second bias currents (I.sub.1, I.sub.2) of known relative proportions (K:1) through the respective first and second transistors. A voltage comparator (26) is arranged to compare a first predetermined fraction (R(R+r)) of the base-emitter voltage of the first transistor (Q1) with a second, larger predetermined fraction (1) of the base-emitter voltage of the second transistor (Q2) so that an output (28) of the comparator assumes a first state when the temperature of the two devices is above a known threshold temperature and assumes a second state when the temperature of the two devices is below the known threshold temperature. The circuit is accurate and is compatible with MOS technology.

Temperature threshold sensing circuit

A filter circuit (2) is automatically tuned so that the positions of the poles and zeros of its frequency response characteristic are maintained in substantially fixed ratios to an input frequency (f.sub.r). The arrangement comprises a frequency discriminator (1) having its output (5) coupled to a controllable element (8) of a resonant circuit included therein, so that the resonant frequency of the resonant circuit is maintained equal to the input frequency. The output 5 also controls a counterpart (13) to element (8), which counterpart is included in an auxiliary circuit (3). The filter circuit is tuned by controlling an element (10) included therein, which element also has a counterpart element (14) included in the auxiliary circuit, both of these elements (10,14) being controlled by the auxiliary circuit output signal. The auxiliary circuit output signal is determined by the ratio between parameters of the respective counterpart elements (13,14), which correspond to parameters of the tuning elements (8,10) which govern the tuning frequencies, and acts to maintain this ratio, and hence the aforementioned ratios, substantially constant.

Filter circuit with automatic tuning

An 'all-pass' filter circuit for use, for example, as a delay section in an integrated circuit, and which should therefore be as simple and as little susceptible to production spreads as possible, comprises first and second long-tailed pairs of transistors (1, 2 and 3, 4 respectively) provided with input emitter followers (26, 28, 30, 32). The pairs are interconnected to form a gyrator having first and second ports (24 and 25 respectively). The first port is loaded by a first capacitor (17) shunted by a damping resistor (22) and the second port is loaded by a second capacitor (18). An input terminal (20) is coupled to the first port via one transistor (1) of the first pair and the relevant emitter follower (26), and the first port is coupled to an output terminal (21) via both transistors (3, 4) of the second pair and the relevant emitter follower (30). A portion of the input signal is added to the output signal in a suitable phase via a second resistor (23) which connects the emitter of the input emitter follower (20) to the emitter of the fourth, grounded-base, emitter follower (32) the collector of which is connected to the output terminal (21). The value of the second resistor is chosen so that the arrangement constitutes an 'all-pass' filter circuit. If desired the collector connections of the transistors of the first pair may be interchanged provided that those of the transistors of the second pair are also interchanged. If desired the emitter followers may be omitted, the second resistor then being connected between the emitters of the first transistor (1) of the first pair and the second transistor (4) of the second pair.

'All-pass' filter circuit including an integrable band-pass filter

In order to facilitate its construction as in integrated circuit, the inductive elements of two resonant circuits in a band-pass filter are each constituted by a first port of a respective gyrator circuit (22, 23 and 24, 25 respectively) the second port of which is loaded by a capacitor (3 and 6 respectively). The first ports, across which are connected capacitors (1 and 3 respectively), are connected by a signal path one to the other, as are the second ports, in such manner that a loop is formed comprising the two gyrator circuits and the two signal paths, enabling bilateral coupling of the two gyrator circuits to be obtained by coupling otherwise unused outputs (24+ and 22+) to otherwise unused inputs (22- and 24- respectively) of two-input two-output voltage-controlled current sources (22, 24) which form part of each gyrator circuit.

Pass filter circuit arrangement

In a filter circuit a reactance is simulated by a voltage amplifier the input of which is connected across a reactive element and the output of which is connected in series with that element, thereby enabling, for example, the series arrangement of a pair of inductances to be simulated by a single capacitively-loaded gyrator (15, 16, 7) and a voltage amplifier (15, 8). The circuit shown simulates a series-resonant circuit fed via a series inductor and is suitable for use as a sound trap in a television receiver. A current proportional to the voltage across the unloaded port (8) of the gyrator (15, 16) generates a corresponding voltage across a load resistor (12) and this voltage is injected effectively in series with any voltage present across a pair of input terminals (1, 2) by means of a differential voltage amplifier (13).

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Horley, United Kingdom

Kenneth W Moulding