Mentor Graphics Corporation

Siemens Industry Software Gmbh

Thinking Machines Corporation

T. M. Patents, L.p.

Kenneth W Crouch

Charles W Selvidge

Vipul Kulshrestha

Guy Lewis Steele, Jr

David C Douglas

Brewster A Kahle

Clifford A Lasser

Matthew L Dahl

Muralidhar R Kudlugi

Alexander D Vasilevsky

Laurent Vuillemin

Soha M N Hassoun

Ansuman Prusty

Harry Mark Bromley

David Bruce Gingold

Twinkle Jain

Shaw W Yang

David P Christman

A system and method for software checkpoint-restoration between distinctly compiled executables is disclosed. A first compiled version of the software, such as Version A, is executed. After which, checkpointing is performed in order to generate a checkpoint image. After checkpointing, restarting execution is performed with at least some of a second compiled version of the software, such as Version B, being executed using a switching function that is configured to switch execution upon restart at least partly to the second compiled version of the software. In this way, different executable versions may be used during the restart than during the initial execution, such as an unoptimized build during the restart versus an optimized build during the initial execution, so that software testing and/or debugging may be performed more efficiently.

Software checkpoint-restoration between distinctly compiled executables

Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification. A path-breaking circuit device is inserted into a location of a design path configured to generate a stall signal indicating whether a change of signal between a pair of neighboring clock cycles of a clock signal is detected at the location. The stall signal is used to directly or indirectly suppress, when the change of signal between the pair of neighboring clock cycles is detected, the next state updating for state element models in the hardware model of circuit design. The design path is usually the critical design path. The insertion location is usually selected to be a location where the signal does not change frequently.

Selective conditional stall for hardware-based circuit design verification

A method allows two substantially asynchronous system components of a logic emulation system to exchange data packets with reference to a clock signal of predetermined frequency. In one example, each bit is transmitted across the system components over two or more cycles of the clock signal. The reference clock signal can be distributed to the two system components from a common clock signal generator, or can be generated locally independently.

Non-synchronized multiplex data transport across synchronous systems

An apparatus and method for efficiently mapping elements of an array to processing elements (PEs) of a parallel data computer. Axis lengths and weights are received from a compiler (if invoked at compile time) or an application program (if invoked at run time). A physical grid is generated by expanding the axis lengths so that their product is integrally divisible by 'machine.sub.-- bits' (i.e., log.sub.2 (number of PEs on the data parallel computer)). The physical grid is divided into subgrids of equal size by dividing each expanded axis length into subgrid lengths of equal length. The lengths and numbers of subgrid lengths in each axis are then output to the compiler or the application program. From the subgrid lengths, the compiler or application program can identify a unique location in one of the subgrids given any location of an element in the array. From the number of subgrids in each axis, the compiler or application program can identify a unique memory location on a unique PE given the subgrid and location identified from the subgrid length.

System and method of mapping an array to processing elements

A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors. In accordance with a preferred embodiment of the invention, three or more transposers are used in connection with each word-oriented processor so as to provide a pipelining capability that significantly enhances processing speeds.

Method and apparatus for interfacing bit-serial parallel processors to a

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Cambridge, MA, United States of America

Kenneth W Crouch