Terarecon, Inc.

Digital Equipment Corporation

Kenneth W Correll

Hugh C Lauer

Vikram Simha

Charidimos E Gasparakis

Larry D Seiler

James M Knittel

William R Peet

Hanspeter Pfister

Joel James McCormack

Christopher C Gianos

Takahide Ohkami

Christopher J Kappler

Jan C Hardenbergh

Vishal C Bhatia

Jay C Wilkinson

Stephen R Burgess

Beverly J Schultz

Barton W Berkowitz

Stephen F Mason

A method renders a volume data set as an image in a volume rendering system. The volume data set includes a plurality of voxels stored in a memory. The volume rendering system includes a plurality of parallel processing pipelines. The image includes a plurality of pixels stored in the memory. A set of rays are cast through the volume data set. The volume data set is partitioned into a plurality of sections aligned with the sets of rays. Voxels along each ray of each set are sequentially interpolated voxels in only one of the plurality of pipelines to generate samples only as long as the samples contribute to the image.

Early ray termination in a parallel pipelined volume rendering system

A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.

Volume rendering integrated circuit

A method generates a histogram of a volume data set in a rendering pipeline. The volume data set includes a plurality of samples stored in a memory. Each sample is partitioned in parallel into a plurality of field according to a plurality of format registers, there is one format register for each field. Entries of a plurality of tables are indexed in parallel with the plurality of fields, there is one entry indexed in each table by each field. The indexed entries are incremented to accumulate a histogram of the fields of the samples of the volume data set.

Method and apparatus for generating a histogram of a volume data set

A method maps samples in a rendering pipelines. The samples are stored in a sample memory. Each sample has a plurality of fields. A descriptor is stored for each field in a field format register. Each sample is read from the memory into a mapping unit. The fields are extracted from each sample according to the corresponding descriptor, and forwarded in parallel to the rendering pipeline.

Method and apparatus for mapping samples in a rendering pipeline

A volume rendering pipeline includes a plurality of processing stages such as a gradient estimation stage, an interpolation stage, a classification stage, an illumination stage, and a compositing stage. The stages are connected to each other by multiplexers. A first multiplexer connects an output of a first stage to an input of a second stage. A second multiplexer connects an output of the second stage to an input of the first stage. A third multiplexer has inputs connected to the output of the first stage and the output of the second stage, the first, second, and third multiplexers are responsive to a select signal to configure the stages of the rendering pipeline for processing the volume data set.

Configurable volume rendering pipeline

A two-level skewing architecture is imposed on the memory subsystem of a volume rendering system in which voxel data is stored in mini-blocks assigned to a set of DRAM memory modules, thereby permitting data transfer at the maximum burst rate of the DRAM memory and enabling real-time volume rendering. Within each DRAM module, mini-blocks are assigned to the memory banks so that consecutively accessed mini-blocks are assigned to different banks, thereby avoiding idle cycles during data transfer and increasing DRAM transfer efficiency to nearly 100%. In one embodiment, read-out of voxel data from banks of the DRAM memory proceeds from left to right unless there is a conflict of banks, in which case the read-out order is reversed. A specialized de-skewing network is provided to re-order the voxel data read out from DRAM memory so that the voxels can be processed in the order which they are arranged in the volume data set rather than the order in which they are stored in memory.

Two-level mini-block storage system for volume data sets

A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.

Apparatus and method for providing non-blocking pipelined cache

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Lancaster, MA, United States of America

Kenneth W Correll