Cadence Design Systems, Inc.

Kenneth Tseng

Nishath Verghese

Igor Keller

Vinod Kariat

Yosinori Watanabe

Alex Kondratyev

A method to analyze and correct dynamic power grid variations in an IC includes performing a dynamic power grid analysis of the circuit, identifying an excessive dynamic power grid voltage fluctuation from the analysis, and modifying the circuit to reduce the excessive dynamic power grid fluctuation.

Method to analyze and correct dynamic power grid variations in ICs

A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.

Eliminating false positives in crosstalk noise analysis

A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim net signal transition; and determining a delay change based upon nominal and noisy victim signal transition arrival times at a victim net receiver output.

Robust calculation of crosstalk delay change in integrated circuit design

Static noise analysis simulates crosstalk functional noise by estimating a crosstalk functional noise window and by calculating the propagation of the noise window through a network. For example, the analysis can include simulations of injecting a noise window onto a network, propagating the noise window through the network until it reaches a register, and comparing the noise window with a register's sensitive window. The noise window for the net is calculated based on a duration of time in which noise glitches caused by capacitive coupling to aggressor nets can occur. The noise window is propagated through the net in a forward direction until the noise is attenuated or reaches a register's input. At the register's input, a sensitive window can filter the noise window so that only the portion of the noise window that coincides with the register's clock trigger time is considered in the noise analysis.

Growing community of inventors

Cupertino, CA, United States of America

Kenneth Tseng