International Business Machines Corporation

Other

K-tor LLC

Kenneth Torino

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Scott Whitney Gould

Alvar Antonio Dean

Robert Maurice Houle

David K Balkin

David-Henry Oliver

A quick release coupling is incorporated into the drive train of the bicycle to couple the crank to the drive shaft. It includes an axle with a flat keyway facilitating installation. A crank arm has an opening matching the circumference of the shaft other than at the flat area. The opening includes a protrusion engaging the keyway to transmit torque. A land is near an end of the shaft. Each coupling has an opening similar to the opening through each crank arm. The orientation of the coupling is with the flat region aligned with the keyway. In this orientation, the coupling is slid over the end of the shaft until the flat area is aligned over the land. The coupling may be rotated until the flat area is misaligned with the keyway and within the land. In this position, the crank arm is locked.

Quick release coupling for the crank of a bicycle drive train

A portable power generator employs high voltage DC, at standard AC voltages and using standard AC connectors. Since switching chargers immediately rectify the 120-240 Volt single phase AC input, a 120-240 Volt DC source is acceptable to drive these chargers. A high frequency conversion to AC and a step up transformer is one approach and the second approach uses an inductor in a boost circuit. Mechanically a hand crank and pedal powered mechanism are used. In a first embodiment, a one dynamo (generator) 10 watt hand crank model can drive the charger for a complete range of portable devices except laptops. In a second embodiment, a two dynamo (generator) model operated with pedals can drive a small 20 watt laptop. The invention contemplates use of either one generator or two generators in parallel or in series. Additional generators over two can also be employed.

Portable power generator

According to the present invention, an automated method to tailor an ASIC core to meet the needs of an individual system on a chip design is disclosed. The preferred method starts with a technology-independent hardware description language (HDL) representation of the core des i on. This high-level design is subdivided into functions, or blocks. Blocks which cannot be removed without impacting the integrity of the core design an are ta b y ed with &ldquo;must-keep&rdquo; indicators. The execution of all application code that will employ the core is simulated on the high-level model. The simulation process accumulates information about what blocks in the model are used by the application code, and which are unused, information about which blocks are unused is combined with information about what blocks are not removable. The high-level core design is then tailored by deleting blocks in the core design that are both unused and removable. The tailored high-level design is then synthesized to a technology-dependent core design. The synthesis process substitutes gates for the blocks, propagating must-keep tags to all gates substituted for a block tagged with a &ldquo;must-keep&rdquo; indicator. The simulation of all application code is repeated on the low-level design, and accumulates information about which gates are unused by the application code. The low-level design is then tailored by deleting Yates in the core that are both unused and removable.

Toggle based application specific core methodology

A method of cache testing and fault correction is implemented subsequent to wafer dicing. Cache testing is moved from wafer level to the built-in self test (BIST) at machine level. The BIST is utilized along with cache redundancy for fault correction. The processor initiates a cache line test using BIST upon power-up. When the processor is powered up and the test mode pins are set for the array test, the array BIST test begins. The BIST traverses the array and tests each word line for hardware faults. Upon detection of a fault, the current address is stored in one of N fault address registers contained in the processor. These fault address registers are used to address redundant cache lines and therefore act as 'soft' fuses. The entire cache structure is traversed in this manner with the addresses of any line faults being stored. If the number of found faults, indicated by stored addresses, are less than the number of redundant fault lines, then the processor self test will proceed to the next test. However, if the number of faults exceed the maximum number N of redundant fault registers, then an error condition will be broadcast to either a set of pins or registers, and the cache will not be allowed to be enabled.

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Colchester, VT, United States of America

Kenneth Torino