Analog Devices,inc.

Kenneth T Deevy

Philip Eugene Quinlan

Peter Real

Mairtin Walsh

Patrick Griffin

A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a 'one of' circuit driving a ROM encoder stage. The ROM constitutes a 'one-of' to Gray- or modified Gray code encoder, or a 'one-of' to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a V.sub.DD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source 'on' resistance, R.sub.on, and obtain a 'low' output voltage when sparkle codes occur. Each bit line is connected to a buffer inverter whose trigger point is scaled to operate with a bit line that can only swing as high as V.sub.DD -V.sub.T (i.e., one threshold voltage below the supply voltage, V.sub.DD) when the bit line is connected to a logical 1. There is high noise immunity because the bit lines are always driven and do not float at high impedance. Static current is drawn only when there is a thermometer code bubble, causing bit cell transistors to contend for control of a bit line. Otherwise, current is needed only during switching.

Rom encoder circuit for flash ADC'S with transistor sizing to prevent

A differential string DAC is provided including a coarse DAC which includes a plurality of coarse resistors connected in series between first and second reference voltage leads. A positive sub-DAC includes a plurality of positive sub-DAC cells, each positive sub-DAC cell including a multitude of series-connected fine resistors. A negative sub-DAC includes a plurality of negative sub-DAC cells, each negative sub-DAC cell including a multitude of series-connected fine resistors. Each coarse resistor is electrically connected in parallel with one positive sub-DAC cell and one negative sub-DAC cell. The positive sub-DAC cell and negative sub-DAC cell are substantially symmetrically disposed about the corresponding coarse resistor. Due to the differential arrangement and symmetrical layout of the DAC, INL errors due to process gradients in one direction across the DAC are greatly reduced. Process gradients in a second orthogonal direction are not of great concern as they cause much smaller INL errors.

Differential string DAC with improved integral non-linearity performance

A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes an input terminal for sequentially receiving a plurality of input signal bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminal, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. An ADC, coupled to the demodulation circuitry, sequentially converts each demodulated signal. The ADC converts a first demodulated signal corresponding to the first of the plurality of input signal bursts before the demodulation circuitry completes demodulating the next of the plurality of input signal bursts. In a preferred embodiment, the ADC converts a demodulated signal corresponding to a first input signal burst while the demodulation circuitry demodulates a signal corresponding to a second, and subsequent, input signal burst. Thus, a pipelined demodulation and conversion scheme is disclosed in which time delays between demodulation and conversion are reduced. In the preferred embodiment, the demodulation circuitry includes area detect circuitry having an integration circuit and a single track-and-hold amplifier.

Pipelined demodulation and ADC conversion scheme for disk drive servo

A comparator for use in an A/D converter such as an algorithmic type. The circuit includes a push-pull inverter gain stage having two series-connected MOSFETs. The input of this inverter is driven by a signal from a preceding current-comparison stage where an input current is compared to a reference current to set the signal level on an input node of the inverter. The trigger point of the inverter is altered by an additional MOSFET, connected in parallel with one of the inverter MOSFETs, and having its gate controlled by the output of a bias voltage control circuit. This circuit includes a control inverter stage matched to the comparator inverter and driven by a control current-comparison circuit matched to the corresponding comparator current-comparison circuit. The input and output nodes of the control inverter are connected to the inputs of an op-amp the output of which controls the gate voltage of an additional MOSFET in parallel with one of the control inverter MOSFETs so as to force the input and output nodes to be of equal voltage. The resulting op-amp output signal serves as the bias signal for the additional MOSFET in parallel with one of the comparator inverter MOSFETs, and sets the trigger point of the comparator inverter at a level equal to the balance point of the preceding current-comparison stage, thereby assuring fast transition times.

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Limerick, Ireland

Kenneth T Deevy