Freescale Semiconductor,inc.

Kenneth Stebbings

Daniel B Schwartz

Vivek Bhan

Bing Xu

Norman Beamish

Sean Francis Sexton

Michael Crowley

A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit. The clock signal selector selectively provides to the output of the clock signal generating arrangement as the system clock signal the compensated reference clock signal when an error in the reference clock signal reaches a first predetermined threshold and until the error in the reference clock signal has been compensated and otherwise the reference clock signal when the communication device is operating in an idle mode or the main clock signal when the communication device is operating in an active mode.

Clock signal generating arrangement for a communication device

Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference between the second time and the first time is less than a threshold time period, the method comprises generating a first message that is representative of the first signal and the second signal and transmitting the first message over the serial interface. In accordance with one embodiment, the threshold time period is equal to one half of an interface acquisition delay time period associated with the serial interface.

Methods and systems for combining timing signals for transmission over a serial interface

Systems and methods are provided for controlling headroom of an amplifier (e.g., in a transmitter). A method comprises obtaining a target output power for a current interval and obtaining a target headroom for a subsequent interval. The method continues by adjusting, during the current interval, the power output capability of the amplifier based on the target headroom and adjusting the input power of an input signal based on the target output power, such that the output power of the amplifier is substantially constant during the current interval as the power output capability of the amplifier is adjusted.

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Grayslake, IL, United States of America

Kenneth Stebbings