Applied Micro Circuits Corporation

Kenneth Smetana

Bruce H Coy

Shyang Kye Kong

A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase detector, generating a phase and reference signals; accepting an adjust signal; modifying the amplitude of the phase signal in response to the adjust signal; integrating the amplitude modified phase signal; using the integrated signal as a phase adjusted signal; integrating the reference signal; using the integrated reference signal and phase adjusted signal to generate a voltage controlled oscillator (VCO) signal; at the Hogge phase detector, accepting the VCO signal as the clock signal. Some aspects of the method further comprise: using the VCO signal to sample data at a settled first phase of the clock; changing the adjust signal; and, using the VCO signal to sample data at a settled second phase of the clock.

Hogge phase detector with adjustable phase output

A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee ) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee ) that is approximately equal to Vcc&minus;(0.4&plus;(level of series gated logic)(0.9 volts)).

Power efficient emitter-coupled logic circuit

A high speed phase detector utilizes an integrated XOR/SUMMER/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/SUMMER/MUX circuit combines the functionality of two parallel XOR devices in series with a summer/multiplexer in a manner that reduces the number of gate delays associated with the input signals. In a practical implementation, the XOR/SUMMER/MUX circuit includes XOR arrangements having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/SUMMER/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Integrated XOR/summer/multiplexer for high speed phase detection

A high speed phase detector utilizes an integrated XOR/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/MUX circuit combines the functionality of an XOR device in series with a multiplexer in a manner that increases the bandwidth of the function. In a practical implementation, the XOR/MUX circuit includes an XOR arrangement having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Integrated XOR/multiplexer for high speed phase detection

An output circuit is provided which exhibits a waveform having a higher edge rate, with less ringing and power consumption than many conventional differential amplifier output driver circuits. A pre-driver stage using a current-mode logic (CML) design eliminates the frequency dependent transfer characteristics associated with emitter follower amplifiers used with emitter-coupled logic (ECL)-pre-drivers. The final stage CML circuit has been modified to eliminate the Miller-effect capacitance, using cascode transistors to maintain a constant voltage at the collectors of the final stage CML circuit transistors. The cascode transistors isolate the switching noise of the final stage CML transistor pair. Further, the bases of the final stage CML transistors present a smaller load to the pre-driver stage output, permitting the pre-driver stage to be a CML rather than an ECL design. A method of amplifying a differential signal in accordance with the principles of the above-described circuit is also provided.

Differential output driver circuit and method for same

An integrated circuit device in which the magnitude of the output voltage swings of outputs in a circuit having emitter coupled output transistors is programmable includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the base of a current source transistor in order to program the magnitude of the output voltage swings. An electrical connection area of the integrated circuit device is connected to the bias voltage generator. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired magnitude of the output voltage swings. The external programming circuit typically can be a resistance or an external voltage source. The variable bias generator can be any of a number of circuits that produce a bias voltage that is dependent upon the external programming circuit connected to the electrical connection area, and that produce a default bias voltage if no external programming circuit is connected to the electrical connection area. Another aspect of the invention is a method for programming the magnitude of the output voltage swings in an integrated circuit device having emitter coupled output transistors. The invention provides the ability to program the magnitude of the output voltage swings of the outputs to increase the magnitude of the output voltage swings, or alternatively, to decrease the magnitude of the output voltage swings thereby advantageously saving power and preventing unnecessary heat generation.

Output buffer with programmable voltage swing

A digital multiplexer with low power consumption and a data to output propagation delay of about one gate includes a plurality of pairs of emitter coupled input transistors. The emitters of each pair of input transistors are connected to the collector of a corresponding selection transistor. The emitters of the selection transistors are connected to a main current source. The data at a selected pair of complimentary data inputs is transmitted to complimentary outputs by activating the selection transistor connected to the pair of input transistors corresponding with the selected inputs, thereby connecting the current source in series with those input transistors. The power consumption of the multiplexer is low because the single main current source is used for all of the inputs. Cascode transistors are connected between the collectors of the input transistors and the bases of output transistors. The cascode transistors isolate the bases of the output transistors from the relatively large capacitance associated with the collectors of the input transistors, enabling the output transistors to switch more quickly, which reduces the data to output propagation delay. Additionally, bleed current sources are connected to the emitters of the cascode transistors. The bleed currents keep the cascode transistors always &ldquo;on&rdquo; in a conducting state, which enables the cascode transistors to switch more quickly, thereby reducing the data to output propagation delay. Accordingly, the multiplexer has low power consumption and a short data to output propagation delay.

Multiplexer with short propagation delay and low power consumption

An integrated circuit device having emitter follower outputs with adjustable output currents includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the bases of current source transistors in order to program the output currents. The variable bias generator is connected to an electrical connection area of the integrated circuit device. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired amount of current in the output current sources. The external programming circuit typically can be a resistance or an external voltage source. The variable bias generator can be any of a number of circuits that produce a bias voltage that is dependent upon the external programming circuit connected to the electrical connection area. Another aspect of the invention is a method for optimizing circuit parameters by programming the output currents in an integrated circuit device having emitter follower outputs. The invention provides the ability to program the output currents to advantageously save power and prevent unnecessary heat generation, while maintaining one or more circuit parameters, such as propagation delay, waveform integrity, or jitter, at or above a target value.

Emitter follower output with programmable current

A ramp circuit discharges an output capacitor to generate a substantially linear ramp signal, current injection is used to stabilize the ramp's output, reducing overshooting and ringing. With faster output stabilization, the ramp exhibits significantly faster repetition rates suitable testing high speed components such as RAM, microprocessors, high speed logic, and the like. The ramp includes an output transistor, with its output defining an output node coupled to a current source and a charge storage device such as a capacitor. The charge storage device charges when the transistor is 'on'. Namely, when the transistor is turned on, the output charge storage device is coupled to a reference voltage, which charges the device in a fixed time. When the transistor is turned 'off', the charge storage device discharges, aided by the flow of current through the current source, resulting in the linear ramp signal. After the charge storage device discharges, current injection is used to quickly stabilize the ramp's output. Particularly, while the output transistor is turned on, permitting the charge storage device to recharge, a transistor couples a bias current source to the output node. Specifically, the transistor is configured to selectively couple the bias current source to the output node when the output transistor is turned on, or a predetermined time thereafter. Conversely, the transistor selectively decouples the bias current source from the output node when the ramp output arrives within a predetermined threshold value of the target ramp starting value.

Current injected ramp with reduced recovery time background of the

A timing vernier repeatedly generates a timing output signal, which includes a timing event such as a state transition, pulse, etc. Unlike prior timing verniers, the present timing event is capable of significantly faster repetition rates. After the ramp signal is initiated responsive to a trigger signal, it changes from a predetermined starting level at a predetermined substantially linear rate. A digital-to-analog converter (DAC) provides an analog timing select signal and a reset select signal responsive to a digital timing select signal. The reset select signal represents the current timing select signal offset by a predetermined amount. A comparator, coupled to the ramp and the DAC, produces the timing event when the ramp output signal reaches the analog timing select signal. Thus, greater analog timing select signals cause earlier timing events, whereas lesser timing select signals result in later timing events. The delay of the timing event is directly proportional to the analog timing select signal. A threshold sensor, coupled to the ramp and the DAC, provides the ramp's reset signal when the ramp output signal reaches the reset select signal. Since the reset select signal is automatically adjusted to be a fixed offset from the analog timing select signal, the ramp is reset as early as possible, without waiting for the ramp output signal to finish its course.

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San Diego, CA, United States of America

Kenneth Smetana