Texas Instruments Corporation

Raytheon Company

Kenneth S Barron

Jeff M Horslund

Anthony Reid

Jerry D Holmes

Christopher D Collinvitti

Y K Lee

Bernard J Gil

William V Crean

A global positioning system receiver with a system and method for parallel synchronization. The novel receiver includes a correlator having plural demodulator channels for receiving a signal from a first satellite, and a processor for processing the signal from the first satellite using a plurality of the channels. The processor includes a parallel synchronization process for synchronizing the receiver with the signal. In an illustrative embodiment, the processor is adapted to instruct the plurality of channels to track the signal from the first satellite in parallel, each channel using a different timing hypothesis. Only the channel determined to have the correct timing is retained for tracking the satellite. For the first satellite only, the processor also demodulates the hand-over word and determines a GPS transmit time. The parallel synchronization process is then repeated for subsequent satellites in turn.

Global positioning receiver with system and method for parallel synchronization for reducing time to first navigation fix

A low power GPS tracking system. The novel system includes a first circuit adapted to collect samples of a signal for a first predetermined length of time and in accordance therewith generate an output signal, and a second circuit for cyclically powering on the first circuit for the first predetermined length of time and powering off the first circuit, or a portion thereof, for a second predetermined length of time. In an illustrative embodiment, the first circuit includes a receiver adapted to receive a GPS signal and output GPS data samples, and a processor adapted to calculate a navigation solution from the GPS data samples using an integrate and dump signal processing technique.

Low power dissipation tracking architecture for GPS navigation systems

A jamming suppression system which includes a plurality of receivers for receiving electromagnetic radiations and a separate notch filter coupled to each receiver for filtering selected frequencies from electromagnetic radiations received by each of the receivers. In accordance with one embodiment of the invention, a spatial combiner responsive to the outputs of each of the notch filters extracts essentially jam-free information from the electromagnetic radiations. In accordance with a second embodiment of the invention, a plurality of spatial combiners, each responsive to the outputs of each of the notch filters, extracts essentially jam-free information from the electromagnetic radiations. The notch filters are adaptive notch filters for on-line selection of their filtering action. One of the notch filters is a master filter and the remainder of the notch filters are slave filters controlled by the master filter. In both embodiments, spatial filtering action is accomplished using a generalized sidelobe canceler that permits gain (relative to an isotropic antenna) to be preserved in the direction of one or more satellites while casting spatial mulls in the directions of inadvertent friendly or hostile jamming signals.

Jamming suppression of spread spectrum antenna/receiver systems

A method, executed in a microprocessor, for providing a shift-and-add mask, M=m.sub.1, m.sub.2, . . . , m.sub.N-1, m.sub.N, for a pseudo-noise sequence generator ('PNSG'). The PNSG generates a first pseudo-noise ('PN') code, and has N stages, each stage being at one of two states. The PNSG also has an associated shifter for generating a shifted PN code which is the same code as the first PN code, but delayed by K chips. The shifted PN code is generated as the inner product of the shift-and-add mask with the states of the stages of the PNSG. According to the inventive method, a value of K is provided, and it is determined whether K is 0. If K is 0, M is provided such that m.sub.N =1 and, for all n.noteq.N, m.sub.n =0. However, if K is not 0, it is determined whether K is greater than N. If K is greater than N, the remainder, R, of the division D.sup.K-1 /f(D), is determined, where

Method for providing offset mask for pseudo-noise sequence generator

Apparatus for providing a reference pseudo-noise ('PN') sequence, and for providing a secondary PN sequence shifted with respect to the reference PN sequence by a number of chips that can be sequentially shifted. The apparatus includes a first pseudo-noise sequence generator ('PNSG'), the PNSG generating the reference PN code, having N stages, each stage being at one of two states, and having a feedback loop from the output of the PNSG, the value on the feedback loop being stored in each stage 1, 2, 3, . . . N, after being multiplied by a constant associated with the stage, C1, C2, C3, . . . CN, respectively, and the result added to the value in the previous stage, with '0' being deemed to be the value in the stage previous to the first stage, and then stored in the stage. Also provided is a mask generator/shifter comprising a second PNSG having N stages, wherein the N stages of the second PNSG may be loaded with a shift-and-add mask, M=m.sub.1, m.sub.2, . . . m.sub.N-1, m.sub.N. A plurality of N logical AND steps are provided, each logical AND step being connected to multiply the states of the corresponding stage of the first PNSG and of the second PNSG. Finally, a plurality of logical XOR steps is provided, connected to add the results of all of the N logical AND steps to provide the secondary PN sequence.

Efficient offset mask generator for pseudo-noise sequence generator

A method for setting the state of a clock-driven pseudo-noise sequence generator ('PNSG') having N stages, after the clock has been inhibited for a predetermined number K of clock cycles, to the state S.sub.2 (D) the PNSG would have been had the clock not been inhibited, based on the state S.sub.1 (D) the PNSG is in at the time inhibition of the clock is commenced. The method involves performing the following steps. First, a previously determined value, a(D)=the remainder of D.sup.Kq /f(D), is stored, wherein D is the delay transform operator, q=2.sup.N -2, and f(D)=c.sub.1 D.sup.N +c.sub.2 D.sup.N-1 + . . . +c.sub.N D+1. The product S.sub.2 (D)=a(D)S.sub.1 (D) is formed, wherein S.sub.1 (D)=s.sub.11 D.sup.N-1 +s.sub.12 D.sup.N-2 + . . . +s.sub.1N D.sup.0. If the degree of S.sub.2 (D) does not exceed N-1, the state bit values for S.sub.2 (D) are inferred from the product. However, if the degree of S.sub.2 (D) exceeds N-1, the product S.sub.2 (D) is first reduced by f(D), and then the state bit values for S.sub.2 (D) are inferred from the product.

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Plano, TX, United States of America

Kenneth S Barron