Hewlett-packard Company

Agilent Technologies, Inc.

Keysight Technologies, Inc.

Kenneth Rush

Ken A Nishimura

Steven D Draving

Thomas F Uhling

Michael Thomas McTigue

David J Dascher

David Eskeldson

Keith C Griggs

Eldon C Cornish

Michael J Lujan

Bob Kimura

Steve Draving

Joshua Webb

Luca Tonini

A system for synthetically sampling an input signal to provide a sampled signal includes a sample clock and a mixer. The sample clock is configured to generate a sampling signal having a sampling frequency. The mixer is configured to receive the sampling signal and the input signal, and to output an intermediate frequency (IF) signal by mixing the sampling signal and the input signal. An offset voltage is introduced into the mixer with the sampling signal to provide a baseband image, the offset voltage being adjusted so that the baseband image of the IF signal has the same magnitude as a first harmonic image of the IF signal.

Method and system for synthetically sampling input signal

A method of calibrating a reconstructed signal from a plurality of sub-signals is provided. The method includes injecting a calibration signal having multiple tones into a received input signal; dividing the input signal into a first and second sub-signal, including an overlapping frequency band; performing a first frequency translation by converting frequency components of the second sub-signal; digitizing the first sub-signal and the frequency converted second sub-signal; performing a second frequency translation to reverse the first frequency translation to obtain a reconstructed second sub-signal; and quantifying impairments to the digital first sub-signal and reconstructed second sub-signal caused by differences in magnitude and phase of frequency components within the overlapping frequency band.

Calibrating reconstructed signal using multi-tone calibration signal

A voltage probe includes a first signal lead configured to receive a first signal from a device under test, a first probe-tip network that is coupled to the first signal lead and that has a frequency response that includes a first transmission zero, a first compensation network that is coupled to the first probe-tip network and that has a frequency response that includes a first transmission pole, a second signal lead configured to receive a second signal from the device under test, a second probe-tip network that is coupled to the second signal lead and that has a frequency response that includes a second transmission zero, a second compensation network that is coupled to the second probe-tip network and that has a frequency response that includes a second transmission pole, and a differential amplifier circuit that is coupled to the first compensation network and to the second compensation network, and that is configured to provide a third signal that is responsive to the first signal and to the second signal. Methods and other systems for providing electrical connections to devices under test are disclosed.

Differential voltage probe

A probe apparatus for use with analyzing devices, primarily oscilloscopes and logic analyzers, which uses pole-zero cancellation to provide a probe with low capacitance and wide bandwidth. Pole-zero cancellation enables the probe to have constant gain at all frequencies. In one embodiment, the coaxial cable between the probe tip and the replication amplifier is terminated in its characteristic impedance to provide constant gain at all frequencies regardless of cable length. Use of pole-zero cancellation and thick film technology enables building a probe with a small, durable tip.

Wide-bandwidth probe using pole-zero cancellation

An electrical interconnect between a plurality of output nodes of a first integrated circuit (IC) and a plurality of input nodes of a second IC, the interconnect. A first bond pad located on the first integrated circuit is coupled to the output nodes. A second bond pad located on the second integrated circuit is coupled to the input nodes. A first digital-to-analog converter located on the first integrated circuit and having an output coupled to the first bond pad receives a plurality of binary inputs from the output nodes of the first integrated circuit. A first analog-to-digital converter is located on the second integrated circuit and coupled to the second bond pad and has an output line coupled to each of the plurality of input nodes of the second IC.

Voltage multiplexed chip I/O for multi-chip modules

A programmable logic device including a plurality of programmable atomic logic elements (PALEs) where each PALE has a plurality of data inputs and generates a data output signal. The PALEs are logically arranged as a plurality of hierarchically coupled partitions. Each partition is defined by a unique set of the next lower hierarchy partitions and an interconnect bus that extends only to the unique set of the next lower partitions that are within that partition. The lowest level of hierarchy is one of the plurality of PALEs. A plurality of hyperlinks provided within each PALE programmably couples the PALE data output signal to each of the interconnect busses in each of the higher levels of hierarchy that include the PALE. Preferably, the PALE also includes a tunnel connection for coupling the PALE data output signal to adjacent neighbor PALEs without using the interconnect bus of any of the partitions.

FPGA with hierarchical interconnect structure and hyperlinks

A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.

High-density wirebond chip interconnect for multi-chip modules

An analog electronic test probe includes hundreds of inputs each connected to two amplifiers, each in a separate multiplexer stage on an integrated circuit. A programmer, responsive to a dial, shifts data through a shift register of latches each of which is connected to one of the amplifiers, activating the amplifier(s) connected to the selected input, thereby multiplexing it (them) to selected output(s). Similarly, the gain for each output may be selected. An outdisable circuit connected to the outputs of each multiplexer and the outputs of each IC chip causes each output to appear electrically as an open circuit when no input associated with the multiplexer or chip is selected. This permits any number of multiplexers and IC chips to be daisy-chained together.

Multiplexing electronic test probe

Disclosed is an analog to digital conversion system that converts high speed analog signals to digital values without using a hold circuit. The system has a narrow aperture sampling circuit that samples an input signal and feeds the sampled signal to a capacitor. A resistor in parallel with the capacitor discharges the capacitor at a predetermined rate, thus the capacitor does not hold the sampled signal. The discharging signal output of the capacitor-resistor circuit is amplified and then filtered using a low-pass filter, which has essentially linear phase shift and no undershoot. The filtered signal is then amplified and fed to a flash analog to digital converter which converts the signal into a digital value. The low-pass filter creates a Gaussian output and the converter is timed to convert the signal at the peak of the filter output.

High speed sampling and digitizing system requiring no hold circuit

A probe apparatus for use with analyzing devices, primarily oscilloscopes, which uses pole-zero cancellation to provide a probe with low capacitance and wide bandwidth. Pole-zero cancellation enables the probe to have constant gain at all frequencies. In one embodiment, the coaxial cable between the probe tip and the replication amplifier is terminated in its characteristic impedance to provide constant gain at all frequencies regardless of cable length. Use of pole-zero cancellation and thick film technology enables building a probe with a small, durable tip.

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Colorado Springs, CO, United States of America

Kenneth Rush