Hrl Laboratories, LLC

Other

Hughes Electronics Corporation

Kenneth Robert Elliott

David H Chow

Daniel Yap

Peter David Brewer

Rajesh D Rajavel

Jose Cruz-Albrecht

George C Valley

Yakov Royter

Chanh Nguyen

Daniel P Docter

Stephen Thomas, Iii

Alan R Kost

A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom surfaces, at least two recesses extending into the channel layer from the top surface of the channel layer and forming a channel region between the at least two recesses, a gate electrode disposed in each of the at least two recesses, and a drain region and a source region formed in the channel layer on opposite sides of said channel region.

P-type diamond gate-GaN heterojunction FET structure

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

Method and apparatus for digital modification and/or modulation of optical signals

The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherein alignment targets on the base semiconductor are used for precise lateral positioning of device structures above.

Method of transistor level heterogeneous integration and system

Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, C. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

Low power bipolar transistors with low parasitic losses

A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic base region separated from the regrown emitter region. The thickness of the extrinsic base region is greater than the thickness of the intrinsic base region.

Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor

In one embodiment of the present invention, an amplifier circuit is provided which includes a predistorter coupled to a power amplifier. An error detector is coupled to the signal input of the predistorter via a delay circuit and to the power amplifier output. The error detector output is coupled to a delta-sigma modulator and the output of the delta-sigma is coupled to the control input of the predistorter. The predistorter may be constructed to provide an output selected from a set of output characteristic curves, in response to a control signal at the control input. The control input of the predistorter may be a multi-bit discrete input, which may be a binary input, such as for example, a three bit binary input.

Amplifier linearization using delta-sigma predistortion

A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphorus. The transistor further comprises, between the substrate and emitter layer, a subcollector layer, a collector layer, a base layer, and an optional spacer layer. The emitter layer may include a graded portion. A contact layer is formed on the emitter layer to provide contacts for the device.

Low base-emitter voltage heterojunction bipolar transistor

A high unity current gain frequency composite switching device, having high voltage compliance and capable of handling high power signals. A current switch comprising of the composite switching devices including a switch stage implemented in a InP-HBT technology and a cascode stage implemented in a GaN FET technology. A digital-to-analog converter comprising a plurality of the current switches, wherein selected output of the switches are electrically coupled to form an output of the digital-to-analog converter.

High efficiency, high output drive current switch with application to digital to analog conversion

An integrated optical transmitter includes a modulator drive circuit in communication with a modulator, and a laser drive circuit in communication with a laser. The modulator receives laser light from the laser and modulation control signals from the modulator drive circuit, and outputs modulated optical signals in a direction normal to the substrate surface. The transmitter is integrated by securing the laser to the modulator using flip chip technology. The laser includes a vertical cavity, and is optically aligned with the horizontal coupling surface of the modulator during the flip chip process.

Integrated optical transmitter

A method of making material layers for semiconductor devices by metal organic vapor phase epitaxy includes the steps of wafer preparation, oxide desorption, growth and post growth with an accompanying reduction of a residual sheet charge at the substrate-epitaxy interface. During the oxide desorption step, a substrate is heated to a temperature minimlly necessary to remove oxide from the substrate. In accordance with such method, material layers for a low noise high electron mobility transistor (HEMT) can be grown without a bulk, buffer layer immediately adjacent the substrate. Rather, a super lattice structure is immediately adjacent to and between the substrate and a channel layer.

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Thousand Oaks, CA, United States of America

Kenneth Robert Elliott