U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Chimei Innolux Corporation

Kenneth R Whight

David J Coe

John A Slatter

Keith M Hutchings

Christopher J Goodings

Martin L Mee

Richard J Tree

A display device with touch sensor input has a touch sensor structure on top of the display layer. The touch sensor structure includes a first and second array of electrodes, the electrodes in the first array being non-parallel to the electrodes in the second array. The first and second arrays of electrodes occupy different fractions of a touch sensor area. These asymmetric fill factors give improved sensitivity.

Display device with touch screen

A method and apparatus for correcting video data signals for addressing an active matrix electroluminescent display device wherein input video signals are modified in accordance with stored electrical characteristic parameter values for each drive transistor () employed to control the current through a respective display element (). The stored values are continually updated to ensure accurate data signal correction which counteracts variations in the electrical characteristics of each drive transistor such as threshold voltage drift, for example. A power line () supplies current to n display elements (). Thus, n sets of data relating to the current through the power line are collected during normal operation of the display, for example. The data is used to calculate updated characteristic parameter values for each drive transistor ().

Video data signal correction

A method of transmitting and receiving a spread spectrum signal, wherein a product of a lower bit rate signal and a second PN-code equals the bit rate of a higher bit rate signal, and wherein a first PN-code sequence is used to spread the product or the higher bit rate signal to a predetermined output chip rate signal which is transmitted. At a receiver, the spread spectrum signal is received and demodulated and in a first operation the demodulated signal is correlated with the first PN-code sequence and in a second operation the output from the first mentioned correlating step is correlated with the second PN-code sequence. The demodulated signal is treated as either a higher bit rate signal or a lower bit rate signal based on the first and second correlations operations.

Multibit spread spectrum signaling

A method of detecting, and a receiver for, a spread spectrum signal, in which a chip sequence is sampled () and filtered in a matched filter (), the output of the filter is averaged () over respective samples of successive chip sequences, sub-samples are determined () by interpolating between the averaged samples, and the position of the chip sequence in the spread spectrum signal is determined () by determining the position of closest match between the sub-samples and samples taken at the same interval from a reference correlation function () of the chip sequence. The time of arrival of the spread spectrum signal may be determined by comparison of the position of the chip sequence, or an average of more than one such position, with a time reference. The position of closest match may be determined by correlation.

Method of detecting, and a receiver for, a spread spectrum signal

Spread spectrum receiver

A method of correlating first and second digital signals which both contain series of numerical data values is disclosed together with a computer program, a computer-readable storage medium) and apparatus for the same. The method includes the steps of (a) sequentially calculating products of corresponding numerical data values of the first and second digital signals and providing a cumulative sum thereof; (b) upon deviation of the cumulative sum from between upper and lower thresholds levels, increasing or decreasing the cumulative sum by a predetermined amount so as to return the cumulative sum to between said threshold levels; and (c) providing a correlation parameter as a function of the number of occurrences of deviation of the cumulative sum from between upper and lower thresholds. The correlation parameter may either increase or decrease depending on whether the cumulative sum deviates above the upper threshold level or below the lower threshold level.

Method and apparatus for digital correlation

An electronic navigation apparatus having improved determination of acceleration and higher order kinematic parameters of the apparatus relative to remote transmitters. The apparatus targets multiple carrier tracking channels having different tracking loop response functions, on a remote transmitter and determines the acceleration, and optionally higher order kinematic parameters, relative to the remote transmitter by operating on the frequency outputs from each of the tracking channels.

Electronic navigation apparatus

A semiconductor body has a first region of one conductivity type coupled to a first electrode. A second region of the opposite conductivity type is coupled to a second electrode and is provided within the first region to form a first pn junction with the first region. At least one further region of the opposite conductivity type is formed within the first region and spaced from the second region so as to form a further pn junction with the first region with each of the first and further pn junctions making a contribution to the capacitance of the diode. This capacitance varies during operation of the diode with a reverse-biasing voltage applied between the first and second electrodes. A coupling region of the opposite conductivity type and more lowly doped than the second and further regions provides a resistive path for free charge carriers of the opposite conductivity type between the second and further region and is sufficiently lowly doped that when a reverse-biasing voltage applied between the first and second electrodes reaches a predetermined value, at least part of the coupling region becomes depleted of free charge carriers to interrupt the resistive path and thereby resistively decouple the second and further region so that the capacitive contributions of the first and further pn junctions are no longer coupled in parallel with one another by the resistive path and the overall capacitance of the diode is reduced.

Variable capacitance semiconductor diode

A mask (4) defining at least one window (4a) is provided on one major surface (1a) of a semiconductor body (1). The semiconductor body (1) is etched to define a groove (5) into a first region (2) of one conductivity type through a second region (3) of the opposite conductivity type. A relatively thin layer of gate insulator (6) is provided on the surface (5a) of the groove (5). A gate conductive region (7) of an oxidizable conductive material is provided within the groove (5) to define with the gate insulator layer an insulated gate structure (8) bounded by a conduction channel-defining area (30) of the second region (3). A step (15) in the surface structure is then defined by causing the insulated gate structure (8) to extend beyond the surrounding surface by oxidizing the exposed (7a) gate conductive material to define an insulating capping region (9) on the gate conductive region (3). A layer (10) is formed over the surface structure and etched anisotropically to leave portions (10a) of the layer on the side wall (8'a) of the step (15) defined by the insulated gate structure (8) and to define beneath the portions (10a) third regions (11) of the one conductivity type within the second region (3). An electrically conductive layer (12) is deposited to contact both the second and the third regions (3 and 11).

Method of manufacturing a semiconductor device comprising an insulated

A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5). Means are provided for transmitting light into the semiconductor body via the given surface to enable photogeneration of charge carriers in the vicinity of the photosensitive pn junction(s) (17). The further region(s) may include one or more annular floating regions (6') spaced apart from the main pn junction(s) and each other.

Photosensitive device suitable for high voltage operation

A method of manufacturing an insulated gate field effect transistor is described. The method comprises providing a gate layer (6) on an insulating layer (12) on one surface (4) of a semiconductor body (1) and source regions (2) of one conductivity type within a respective body region (14), a portion of each body region (14) underlying a portion of the gate layer to provide a channel area extending between the source region (2) and a drain region (3) meeting another surface (5) of the semiconductor body opposite the one surface (4). Each source region (2) is shorted to the corresponding body region (14) by opening a contact window (15) in the insulating layer on the one surface so as to expose a surface of the source region (2), providing resist masking regions (16) extending completely across the contact window in one direction so as to define an exposed area of the source region which is not covered by either the masking regions or the insulating layer ( 12), and has a periphery defined partly by the contact window and partly by the masking region(s), etching away the exposed area of the source region (2) to expose an underlying area of the body region (14), removing the masking regions and providing metallization within the contact window (15) to short the exposed area of the body region to the source region.

Method of manufacturing an insulated gate field effect transistor DMOS

A method of manufacturing a semiconductor device in which a conductive layer (6) provided on a surface (4) of a semiconductor body (1) is formed with at least one opening (10). The semiconductor device may be an insulated gate field effect transistor (IGFET) in which case the opening (10) defines a hollow gate structure for the IGFET. Insulating material (16') is grown on the surface (4) to cover the conductive layer. The opening or openings (10) are sufficiently small and the growth of insulating material is continued for a sufficiently long period that insulating material growing on edges (8'a) of the conductive layer bounding the openings (10) meets to close the openings so that subsequent etching of the insulating material anisotropically towards the surface (4) to expose a surface of the conductive layer and/or to form a window (18) within insulating material covering an area of the semiconductor body surface larger than the openings and not covered by the conductive layer, leaves insulating material (19,17) on edges of the conductive layer so that the openings remain closed. Where the semiconductor device is an IGFET impurities to form the source and channel regions may be introduced via the window.

Method of manufacturing a DMOS device

A semiconductor diode includes a semiconductor body having a first region (1) of one conductivity type, a second region (2) of the opposite conductivity type meeting only a given surface (4) of the body and surrounded by the first region (1) so as to form with the first region (1) a first pn junction (3) which, when reverse-biassed in operation of the diode by a voltage applied across the diode, gives the diode a blocking characteristic, and a third region (15) of the one conductivity type more highly doped than the first region (1) provided within the first region (1) for triggering conduction of the diode when a predetermined voltage less than that at which the main pn junction (3) would have broken down in the absence of the third region (15) is applied across the diode to reverse bias the first pn junction. The third region (15) meets only the given surface (4) and a passivating layer (9) on the given surface covers the third region (15). The third region (15) is located such that a depletion region extends from the first pn junction to the third region (15) when a voltage less than the predetermined voltage is applied across the diode to reverse-bias the first pn junction, the predetermined voltage being determined by the relative locations of the second region (3) and the third region (15). The third region (15) may form a breakdown ring with a fourth region (16).

Semiconductor diode

The breakdown voltage of a p-n junction operated under reverse bias in at least one mode of operation of a semiconductor device is increased by providing at least one annular region forming an auxiliary p-n junction within the spread of a depletion layer from the reverse-biased junction. A passivating dielectric layer with an overlying electrically resistive layer extends over the semiconductor body surface between the active device region forming the p-n junction and a surrounding region of the body portion located beyond the (outer) annular region. The resistive layer is connected to these regions but is insulated from the annular regions by the dielectric layer. A stable high breakdown voltage can be obtained by providing the resistive layer with conductive connection means at the or each annular area which overlies the annular region(s). The conductive connection means, which may be for example annular metal areas or annular highly-doped parts of the resistive layer, is more highly conductive than the resistance of adjacent parts of the resistive layer and provides an electrical connection between these adjacent parts so that a potential variation which corresponds approximately with that along the underlying semiconductor body surface (including the annular regions) can be obtained along the resistive layer.

Semiconductor device having an annular region for improved voltage

In order to increase the breakdown voltage of a reverse-biased p-n junction of a semiconductor device, at least three annular regions which extend around the active device region are located within the spread of a depletion layer from the junction. At least one inner annular region is wider than outer annular regions, and this increased width of the inner region or regions reduces peak electrostatic fields found to occur at the bottom outer corners of the active device region and inner annular regions. The spacing of the annular regions increases with remoteness from the active device region, although at least two inner annular regions may have the same spacing as that of the innermost annular region from the active device region. A group of annular regions may have the same width as each other in the group.

Growing community of inventors

Horsham, United Kingdom

Kenneth R Whight