Intel Corporation

Vlsi Technology, Inc.

Kenneth R Smits

Bharat Bhushan

Mahadevamurty Nemani

Eddy C Huang

Shenggao Li

Mohammed E Ul Haq

Edward E Helder

Mahesh M Chheda

Brandon M Walters

Various embodiments of this disclosure may describe a circuit for transmitting data from a transmitting region of an integrated circuit to a receiving region of the integrated circuit. The circuit may level-shift the data to the appropriate voltage level and may have good tolerance to clock skews. Other embodiments, including an integrated circuit having the circuit or a system with the integrated circuit, may also be disclosed or claimed.

Combined data level-shifter and DE-skewer

Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array.

Apparatus and methods for providing enhanced redundancy for an on-die cache

Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of memory cell sub arrays. The sub arrays including a plurality of arrays of memory cells, the arrays including regular arrays and at least one redundant sub array. Logic circuitry is associated with each cache bank. A change in a single bit of the logic circuitry from a first to a second logic state causes one of the regular arrays to become disconnected from the global data bus, and the redundant array to become connected to the global data bus.

Cache architecture with redundant sub array

A cache memory organized into banks of subarrays includes repeaters for connecting to the data provided by the subarrays to a global data bus. The repeaters comprise a logic gate providing either a NAND or NOR function coupled in series with an inverter. The logic gate has a first input connected to receive a first logic value of a bus line, and a second input coupled to receive data output from a subarray. The inverter drives the first logic value onto the bus line when the cache bank subarray is inactive, and drives the data value from the subarray onto the bus line when the cache bank subarray is activate.

On-die cache memory with repeaters

Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.

Cache architecture for pipelined operation with on-die processor

A circuit for testing signatures at a pin in a CMOS device where this device is operable when it is powered by a voltage within the predetermined range. During the test mode, a task voltage whose magnitude is below that of any voltage in the operating range as applied so that parasitic diode turn-on is prevented.

Signature indicating circuit

A static random access memory (SRAM) comprises plural memory cells, a true-bit load and a complementary-bit load, a true-bit line and a complementary bit line, a sense amplifier and an address transition detector. The address transition detector is used to generate load pulses which switch off the loads just after either of the memory cells is selected. This speeds signal development during a read (or write) operation. Since provision is made for modulating the loads, they can be designed to permit larger-than-conventional currents to flow therethrough when maximally on. The loads are maximally on just after cell deselection to facilitate bit-line equalization between cell selections. Thus, the present invention provides for briefer inter-select periods, quicker reads upon cell selection, and, thus, a faster SRAM overall.

Growing community of inventors

San Ramon, CA, United States of America

Kenneth R Smits