Broadcom Corporation

Kenneth R Kindsfater

Fang Lu

Agnes Woo

Zhihui Wang

Tarek Kaylani

Balasubramanian Annamalai

Jeff Echtenkamp

Henry Samueli

Sathish Kumar

Lakshmanan Ramakrishnan

Lionel D'Luna

Anand Pande

According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.

Mask programmable interface selection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range.

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Semiconductor die with mask programmable interface selection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Schmoo runtime reduction and dynamic calibration based on a DLL lock value

System and method for ESD Protection

A direct broadcast satellite sends subscribers signals received from an earth-station transmitter and typically having a 10 MHz bandwidth, 6 MHz for an analog video station and 4 MHz for up to 24 digital audio stations. When a subscriber selects one of the audio stations, an FM demodulator recovers the 10 MHz signal; a variable gain amplifier amplifies the received signal; and an A/D converter digitizes the amplified signal at (e.g.) 24.576 MHz. A digital synthesizer produces trigonometric functions (sine, cosine) at (e.g.) 24.576 MHz, and mixers downconvert the signals to baseband. The sampling frequency is then reduced to 256 KHz, twice the digital audio signal baud rate. In response to the 256 KHz signals, a first servo varies a VCO frequency to obtain a regulation by the A/D converter of the digitizing frequency at 24.576 MHz and another servo regulates the frequency of the trigonometric functions. A microcomputer provides a fixed coarsely amplified gain to the 256 KHz signals dependent upon the relative amplitudes of the video and audio signals. The amplitudes of the coarsely amplified signals are detected, filtered and converted to an analog voltage to precisely regulate the gain of the variable gain amplifier. The sampling frequency of the signals at the outputs of the programmable gain stages is reduced to 128 KHz (i.e. the transmitted baud frequency). A Viterbi decoder corrects errors in these in-phase and quadrature baseband 'soft-decision' signals. The resulting 192 kb/s output data stream is decompressed and converted to stereo audio sound.

Growing community of inventors

Irvine, CA, United States of America

Kenneth R Kindsfater