Actel Corporation, Inc.

Microsemi Soc Corporation

Kenneth R Irving

Venkatesh Narayanan

Ming-Hoe Kiu

Vishal Aggrawal

Prasad Karuganti

Jonathan W Greene

An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Apparatus and methods for in-application programming of flash-based programmable logic devices

Apparatus and methods for in-application programming of flash-based programable logic devices

A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.

Programmable logic device adapted to enter a low-power mode

Secure delivery of configuration data of an intellectual property (IP) core includes the steps of loading configuration data for the IP core into IP core space by an IP core provider, masking portions of the IP core space not loaded with configuration data in the loading configuration data step with the value 0 or 1 by the IP core provider, encrypting data in the IP core space by the IP core provider, loading configuration data for system design other than for the IP core into a remainder space and any unused portions of the IP core space by a system designer, masking portions of the IP core space loaded in the loading configuration data step with the value 0 or 1 used by the IP core provider in the masking portions of the IP core space not loaded step, and encrypting data in a configuration space by the system designer.

Method for secure delivery of configuration data for a programmable logic device

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Austin, TX, United States of America

Kenneth R Irving