Seagate Technology Incorporated

Storage Technology Corporation

Kenneth R Burns

Bernardo Rub

Robert D Cronch

Tim Rausch

Neal Glover

Kinhing Paul Tsang

Keith Gary Boyer

Mai Ghaly

James E Angelo

Clifton James Williamson

Jimmie Ray Shaver

Robert D Thompson

Peter Igorevich Vasiliev

Ke Du

Hossein F Sevvom

Terry R Gottehrer

Robert E Kost

Michael R Stephens

Akhila Tadinada

Gary W Reininga

Thomas H Gohl

Kevin M Bailey

Srinivas Maddali

Wuping Chen

Kavi Alptekin

John W Craig

Paul J Choquette

Bernie R Marasco

An apparatus includes an optical pathway configured to deliver energy to heat a magnetic recording medium via a slider body. The optical pathway generates heat in the slider body when delivering energy to the magnetic recording medium. The apparatus includes a compensating heater with a thermal characteristic that matches a thermal characteristic of the optical pathway. The compensating heater is activated at least part of the time when the optical pathway is not delivering the energy to the magnetic recording medium.

Heat assisted media recording apparatus with compensating heater

A method is provided that decides whether a region of data storage units in a data storage system should be scanned for defective data. A current region of data storage units affected by a write operation is determined and which select transducing head of the data storage system that corresponds with the current region is also determined. A scalar value that corresponds with the select transducing head is retrieved. The scalar value related to a condition of the select transducing head based on previously conducted performance tests. An incremented write count of the affected region is scaled by the scalar value to obtain a new increment write count. A defective data scan is performed on the affected region if the new increment write count exceeds a default write count threshold.

Data recovery scan based on head performance

Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

Configuration of channel-to-controller interface in a disc drive

The present invention provides sequence detection which takes into account amplitude and/or time distortions caused by neighboring magnetization regions on the magnetic medium, wherein the distortions in one magnetization region are caused by the closeness of neighboring magnetization transitions on one or both sides thereof. The sequence detection according to the present invention provides an extended state diagram to include the effects of leading and/or trailing magnetization transitions. More particularly, it has been found that accounting for the effects of trailing transitions requires an increase in the number of states in the state diagram used to form the Viterbi detector. Leading transitions are neutralized by increasing the number of branches between states in the Viterbi detector. Increasing the number of branches instead of states keeps the complexity low and thus saves hardware and associated costs.

Branch metric compensation for digital sequence detection

An apparatus and method are disclosed for reducing the effects of thermal asperities and other anomalous conditions on disc drive read operations. An improved data block format is provided having first and second sync fields in which sync patterns are stored, the first and second sync fields being separated by a selected distance within the data block. The sync pattern of the second sync field enables synchronization of a disc drive read channel to the user data in the data block when the read channel fails to be synchronized by the sync pattern of the first sync field. In one embodiment, control information used by the read channel to prepare for receipt of the user data is stored in a field between the first and second sync fields; in an alternative embodiment, a portion of the user data is stored between the first and second sync fields.

Redundant synchronization fields to improve disc drive read performance

Signal processing circuitry receives input signals representing modulation encoded binary data signals. The signal processing circuitry contains a plurality of signal quality detectors which monitor a corresponding plurality of different characteristics of each received signal to determine whether or not the signal is of an adequate quality insofar as concerns the characteristic of the signal associated with each detector. Each detector generates a binary output signal representing a confidence level pointer associated with each such received signal. The pointer signals are stored in a buffer with received data signals. The contents of the buffer, which at this time contain the bytes of the received data record as well as the associated pointer bytes, are made available to a control module. Only the data and redundancy bytes of the record stored in the buffer are used by the control module if the data bytes are of sufficiently high quality so that any errors in the data bytes can be corrected using the redundancy bytes. If the received data bytes of the record are corrupted so that they cannot be corrected by the use of only the redundancy bytes, the control module reads the data buffer to receive the pointer bits of the record. The pointer bits specify with particularity which data bytes likely, contain errors. The control module uses the received pointer bits together with the redundancy bytes to correct the corrupted data bytes.

Error pointers for enhanced error correction

The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length packets with the packet contents being out of sequential order. The received data is written to a storage device after being restored to the correct sequential order. The data packets are comprised of a header portion and a data portion. The transmission and compression methods commonly employed by the transmission device dictates that the header portion of each packet follows the data portion. The present invention computes a complete CRC code for the data stored in a page buffer in real time as the packets are received by using several registers for saving intermediate CRC codes and circuitry to combine partial CRC codes for those packet portions received out of order. Additional circuitry is provided which reorders the data packet portions received out of order back into sequential order as the data is stored in a page buffer memory in real time. Computing the CRC codes in real time permits the saving of costs associated with other approaches that significantly buffer the incoming packets to permit subsequent reordering and CRC computation. The present invention assures data integrity of data from the time it is received from the compression unit until the time it is sent to the storage device. In addition, the present inventions ability to compute the CRC codes real time maintains optimal performance of data throughput of the storage subsystem. The present invention alleviates problems relating to delaying new data packet transmissions as deferred CRC computations are performed on previous packets reordered in temporary buffer memory.

Apparatus and method for CRC computation over fixed length blocks

The data detection circuit includes a sampling detector which measures both the shape and amplitude of the incoming pulse signal. This apparatus determines the amplitude of the read signal at a plurality of points in time and produces a signal indicative of the presence of recorded data if the measured amplitudes match predetermined thresholds. The predetermined thresholds are used in three measurements: determination that the amplitude of the read signal at one point in time exceeds a predetermined threshold; a determination that the amplitude of the read signal at the one point in time concurrently exceeds the amplitude of the read signal at two other points in time both before and after the one point in time. Also included in this apparatus is a clock generation circuit that produces a clock signal based upon the indication of the presence of recorded data so that the indication of the recorded data and the generation of the clock signal occur in a single channel.

Data detection circuit having a pulse shape and amplitude measuring

Growing community of inventors

Bloomington, MN, United States of America

Kenneth R Burns