Freescale Semiconductor,inc.

Motorola Corporation

Kenneth R Burch

Marc Alan Mangrum

Ravindraraj Ramaraju

Charles Eric Seaberg

William C Moyer

Wendell L Little

Jinbang Tang

James Robert Feddeler

David R Bearden

Darrel R Frear

Jong-Kai Lin

Lawrence N Herr

Mario A Rivas

Robert E Booth

Walter L Davis

Hector Adrian Sanchez

Barry W Herold

Shayan Zhang

Andrew Christopher Russell

William H Lytle

Claude Moughanni

James Andrew Welker

Bradley J Garni

David Patten

John K Mahabadi

Omid Tahernia

Lipeng Cao

Jeffrey D Ganger

Kevin M Traynor

Samuel G Stephens

Mazyar Razzaz

Vincent B Deems

Gordon R Burns

Hengwei Hsu

Carol G Pyron

Ramon V Enriquez

A tool for testing a double data rate ('DDR') memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye. An inspection of the location of the data strobe transition with the data eye may be utilized to show the range of timing steps available before the data strobe transition would fail to capture valid data from the incoming data eye.

Margin tool for double data rate memory systems

Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

Multistage voltage regulator circuit

A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains () having different delay values connected to sampling latches (-) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.

High precision single edge capture and delay measurement circuit

A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.

Memory voltage regulator with leakage current voltage control

A method of forming a semiconductor package includes providing a carrier, attaching a first surface of a first device on the carrier, wherein the first surface comprises a first active surface of the first device, and attaching a second surface of a second device on the carrier. In one embodiment, the second surface is opposite a third surface of the second semiconductor die and the third surface comprises a second active surface. A first insulating material can be formed between the first device and the second device.

Method of forming a semiconductor package including two devices

A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Integrated circuit having low power mode voltage regulator

A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.

Apparatus and method to compensate for injection locking

In one form a device having an integrated circuit is rendered useless by providing a piezo element coupled to a voltage terminal of the integrated circuit of the device. A render useless signal is generated by any of several ways. The piezo element, in response to the render useless signal, renders in any one of several ways the device to be rendered useless. The piezo element, when disturbed, generates a voltage which is provided to the voltage terminal of the integrated circuit, the voltage being sufficiently high to render useless at least a portion of the integrated circuit. In other forms the render useless signal renders MRAM circuitry within the device useless by moving a magnetic field across the MRAM circuitry to vary resistance of memory reference cells. In one form the magnetic field is moved by spring-loading or pivoting a magnet that is released by the piezo element.

Device that can be rendered useless and method thereof

Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Method of making an integrated circuit package with shielding via ring structure

A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.

Circuit for a low power mode

Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Method of packaging a device having a multi-contact elastomer connector contact area and device thereof

A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Test interposer having active circuit component and method therefor

Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. An insulating layer is formed over the first major surface. A via is formed in the insulating layer. A tangible element is coupled to the semiconductor device through the via. At least a portion of the tangible element is surrounded with a cavity wall having a first face toward the element and a second face away from the element. A supporting layer, after surrounding the tangible element, is formed over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face thereby providing protection for the tangible element.

Method of packaging a device having a tangible element and device thereof

A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Growing community of inventors

Austin, TX, United States of America

Kenneth R Burch